Prosecution Insights
Last updated: July 05, 2026
Application No. 18/662,207

METHOD FOR REDUCING DAMAGE TO FLOATING GATE POLYSILICON DURING ETCHING

Non-Final OA §103
Filed
May 13, 2024
Priority
Jun 13, 2023 — CN 202310699681.4
Examiner
RAHAMAN, SHAHAN UR
Art Unit
Tech Center
Assignee
Shanghai Huali Microelectronics Corporation
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
494 granted / 650 resolved
+16.0% vs TC avg
Moderate +13% lift
Without
With
+12.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
35 currently pending
Career history
698
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
74.2%
+34.2% vs TC avg
§102
2.6%
-37.4% vs TC avg
§112
2.4%
-37.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 650 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objection (Allowable Subject Matter) Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Following is a list of prior arts are considered pertinent to applicant's disclosure, including prior arts not relied upon in the rejection US 20110001181 A1 (hereinafter JU) US 20230320089 A1 (hereinafter Shu) US 20230395729 A1 (para 17, 37; Fig.1A-C) J. Pu et al., "Carbon-Doped Polysilicon Floating Gate for Improved Data Retention and P/E Window of Flash Memory," in IEEE Electron Device Letters, vol. 29, no. 7, pp. 688-690, July 2008 Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over JU in view of Shu. Regarding Claim 1. JU teaches a method for reducing damage to floating gate polysilicon during etching, at least comprising: step 1, providing a tunneling oxide layer [(#112, para 33, Fig.10 & Fig.11 )], and forming a floating gate on the tunneling oxide layer, wherein the floating gate has , dividing the floating gate into a first region and a second region, wherein the first region includes a portion of the floating gate from a bottom [(120c having layers 122 and 124 )] step 2, performing carbon doping deposition to the first region of the floating gate, wherein a carbon doping flow rate is arranged to be in gradually decreasing grades in a direction from the floating gate bottom up to [(para 36, 122 is dopped with carbon, 124 is not substantially doped with carbon; Gradient doping profile in para 38 )] step 3, forming a stack layer comprising silicon oxide, silicon nitride, and silicon oxide on the floating gate: [(Fig.10 #130; para 61 )] and step 4, forming a control gate on the stack layer [(#140, para 61 )] JU does not explicitly show that the first floating gate layer is 400 A thick However, in the same/related field of endeavor, Shu teaches the first floating gate layer is 400 A thick [(para 39, Fig.2A; fluting gate bottom layer 210 have a thickness of 400 angstroms )] Therefore, in light of above discussion it would have been obvious to one of the ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teaching of the prior arts because such combination would provide predictable result with no change of their respective functionalities, because both of the prior arts are describing floating-gate structure in a memory device (see respective abstract), therefore the thickness mentioned in Shu would work with JU to work in a memory device. JU additionally teaches w.r.t. claim 2. The method for reducing damage to floating gate polysilicon during etching according to claim 1, wherein the floating gate in step 1 comprises polysilicon. [(JU para 34 )] JU additionally teaches w.r.t. claim 3. The method for reducing damage to floating gate polysilicon during etching according to claim 1, wherein the floating gate in step 1 is formed by a deposition method [(JU para 54 )] Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahan Rahaman whose telephone number is (571)270-1438. The examiner can normally be reached on 7am - 3:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nasser Goodarzi can be reached at telephone number (571) 272-4195. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form. /SHAHAN UR RAHAMAN/Primary Examiner, Art Unit 2426
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Prosecution Timeline

May 13, 2024
Application Filed
Jun 04, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
89%
With Interview (+12.8%)
2y 10m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 650 resolved cases by this examiner. Grant probability derived from career allowance rate.

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