Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
19 pending office actions • 10 art units • 19 examiners • 0 of 19 (0%) have an AI response strategy ready • 51 patents granted in the last 365 days
Shanghai Huali Microelectronics Corporation maintains a large portfolio in the Semiconductors, Circuits & Optics technology area. There are 17 pending office actions currently distributed among 17 distinct examiners. This matching count indicates a highly fragmented prosecution landscape where no single examiner holds a dominant share of the workload. These 17 pending office actions are spread across 8 distinct art units, reflecting a broad technical range within the semiconductor sector.
SLUTSKER, JULIA is identified as the busiest examiner, yet this individual is responsible for only 1 pending office action. This distribution reinforces the fact that the company's legal strategy must account for a wide variety of examiner preferences and art unit specificities. For practitioners, the presence of the pending office actions across 8 distinct art units requires a versatile approach to response drafting. Success depends on navigating the unique requirements of the different examiners across the 8 distinct art units involved.
Based on the USPTO statutory response window for each pending office action. 4 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 4 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 only | 1 (5%) |
| §101 + other | 1 (5%) |
| §103 only | 7 (37%) |
| §112 only | 2 (11%) |
| Multi-statute (no §101) | 8 (42%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| SLUTSKER, JULIA | 1 | 76.8% | +12.9% |
| TRAN, DZUNG | 1 | 83.6% | +5.7% |
| LU, JIONG-PING | 1 | 83.6% | +7.8% |
| ESQUINO, CALEB LOGAN | 1 | 56.7% | +0.6% |
| DAVIS, SEAN MICHAEL | 1 | — | — |
| MANG, LAL C | 1 | 76.0% | +17.2% |
| REAMES, MATTHEW L | 1 | 77.1% | +18.0% |
| PETERSON, ERIK T | 1 | 76.5% | +11.0% |
| BRADFORD, PETER | 1 | 80.7% | +4.3% |
| CHOI, WOO H | 1 | 83.5% | -4.1% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18783249 | METHOD FOR IMPROVING PERFORMANCE OF MOS DEVICE | TRAN, DZUNG | — |
| 18582183 | STATIC RANDOM-ACCESS MEMORY AND INTEGRATED CIRCUIT LAYOUT THEREOF | CHOI, WOO H | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17877324 | Method for Manufacturing Integrated Metal Resistance Layer | PRIDEMORE, NATHAN ANDREW | 1d overdue |
| 18810415 | METHOD FOR FORMING HYBRID SUBSTRATE OF SOI WAFER | SLUTSKER, JULIA | — |
| 18778752 | POLYSILICON GATE ETCH METHOD | LU, JIONG-PING | — |
| 18738394 | SURFACE MODIFICATION METHOD FOR REDUCING WAFER DEFECTS | DAVIS, SEAN MICHAEL | — |
| 18644604 | METHOD FOR REDUCING MEASUREMENT ERRORS IN CRITICAL PATTERN DIMENSIONS OF POLYCRYSTAL LAYERS | MANG, LAL C | — |
| 18614346 | METHOD FOR MANUFACTURING ALUMINUM PAD OF SEMICONDUCTOR CHIP | PETERSON, ERIK T | — |
| 18612961 | SUPER FLASH AND METHOD FOR MANUFACTURING SAME | BRADFORD, PETER | — |
| 18406371 | Wafer Temperature Control System and Control Method, Computer Device, and Storage Medium | NGUYEN, DUSTIN T | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18810415 | METHOD FOR FORMING HYBRID SUBSTRATE OF SOI WAFER | SLUTSKER, JULIA | — |
| 18644604 | METHOD FOR REDUCING MEASUREMENT ERRORS IN CRITICAL PATTERN DIMENSIONS OF POLYCRYSTAL LAYERS | MANG, LAL C | — |
| 18641881 | HIGH-VOLTAGE METAL GATE DEVICE AND PROCESS METHOD FOR THE SAME | REAMES, MATTHEW L | — |
| 18614346 | METHOD FOR MANUFACTURING ALUMINUM PAD OF SEMICONDUCTOR CHIP | PETERSON, ERIK T | — |
| Art Unit | Apps |
|---|---|
| 2897 | 2 |
| 2677 | 1 |
| 2827 | 1 |
| 3723 | 1 |
| 3745 | 1 |
| 2817 | 1 |
| 2851 | 1 |
| 2898 | 1 |
| 2899 | 1 |
| 2857 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18810415 | METHOD FOR FORMING HYBRID SUBSTRATE OF SOI WAFER | SLUTSKER, JULIA | — | §103§112 | Non-Final OA | — | Pending | Aug 20, 2024 |
| 18783249 | METHOD FOR IMPROVING PERFORMANCE OF MOS DEVICE | TRAN, DZUNG | — | §103 | Non-Final OA | — | Pending | Jul 24, 2024 |
| 18778752 | POLYSILICON GATE ETCH METHOD | LU, JIONG-PING | — | §102§103 | Non-Final OA | — | Pending | Jul 19, 2024 |
| 18748253 | METHOD FOR IMPROVING QUALITY OF CDSEM IMAGES | ESQUINO, CALEB LOGAN | 2677 | §103 | Non-Final OA | — | Pending | Jun 20, 2024 |
| 18738394 | SURFACE MODIFICATION METHOD FOR REDUCING WAFER DEFECTS | DAVIS, SEAN MICHAEL | — | §103§112 | Non-Final OA | — | Pending | Jun 10, 2024 |
| 18644604 | METHOD FOR REDUCING MEASUREMENT ERRORS IN CRITICAL PATTERN DIMENSIONS OF POLYCRYSTAL LAYERS | MANG, LAL C | — | §101 | Final Rejection | — | Pending | Apr 24, 2024 |
| 18641881 | HIGH-VOLTAGE METAL GATE DEVICE AND PROCESS METHOD FOR THE SAME | REAMES, MATTHEW L | — | §112 | Non-Final OA | — | Pending | Apr 22, 2024 |
| 18614346 | METHOD FOR MANUFACTURING ALUMINUM PAD OF SEMICONDUCTOR CHIP | PETERSON, ERIK T | — | §102§103§112 | Non-Final OA | — | Pending | Mar 22, 2024 |
| 18612961 | SUPER FLASH AND METHOD FOR MANUFACTURING SAME | BRADFORD, PETER | — | §103§112 | Non-Final OA | — | Pending | Mar 21, 2024 |
| 18582183 | STATIC RANDOM-ACCESS MEMORY AND INTEGRATED CIRCUIT LAYOUT THEREOF | CHOI, WOO H | 2827 | §112 | Non-Final OA | — | Pending | Feb 20, 2024 |
| 18406465 | Wafer Polishing Locating Ring and Chemical Mechanical Polishing Device | DION, MARCEL T | 3723 | §103 | Non-Final OA | 36d | Pending | Jan 08, 2024 |
| 18406371 | Wafer Temperature Control System and Control Method, Computer Device, and Storage Medium | NGUYEN, DUSTIN T | 3745 | §103§112 | Non-Final OA | — | Pending | Jan 08, 2024 |
| 18465011 | METHOD FOR MEASURING THICKNESS OF SILICON EPITAXIAL LAYER | WEGNER, AARON MICHAEL | 2897 | §103 | Non-Final OA | — | Pending | Sep 11, 2023 |
| 18175878 | Method for Manufacturing Metal Zero Layer | DUREN, TIMOTHY EDWARD | 2817 | §103 | Final Rejection | 10d overdue | Pending | Feb 28, 2023 |
| 18175092 | METHOD FOR MANUFACTURING SIGMA-SHAPED GROOVE | JUNGE, BRYAN R. | 2897 | §103 | Non-Final OA | 29d overdue | Pending | Feb 27, 2023 |
| 18154154 | OPC Method | LIN, ARIC | 2851 | §103§112 | Non-Final OA | — | Pending | Jan 13, 2023 |
| 17877324 | Method for Manufacturing Integrated Metal Resistance Layer | PRIDEMORE, NATHAN ANDREW | 2898 | §103§112 | Non-Final OA | 1d overdue | Pending | Jul 29, 2022 |
| 17839313 | METHOD FOR MANUFACTURING METAL GATE MOS TRANSISTOR | NIELSEN, DEREK LANG | 2899 | §103 | Non-Final OA | — | Pending | Jun 13, 2022 |
| 18368137 | Method and System for Analyzing Wafer Angle in Semiconductor Integrated Circuit Manufacturing | WALSH, RYAN D | 2857 | §101§102§112 | Non-Final OA | — | Pending | Sep 14, 2023 |
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