DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response in which claims 1, 9, and 15 are amended has been entered of record.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sivero et al. (US Pub. 2024/0265959).
Regarding claim 1, Fig. 6 of Sivero discloses an apparatus, comprising:
a memory having a group of memory cells [110, 112, Fig. 1], wherein a sub-group of the memory cells of the group are always programmed to a same data state [both cells 110 and 112 were programmed to “1” state, as shows in Fig. 1 and discloses in paragraph 0020] throughout operation of the memory [throughout a programming operation of the memory]; and
circuitry [combination of 120 and 130, Fig. 1] configured to:
determine an amount of charge associated with the memory cells of the sub- group [steps 620 and 620, to read and to determine memory states, which is equivalent to determine an amount of charge]; and
adjust a voltage [step 640] used to sense a data state of the memory cells of the group based, at least in part, on the determined amount of charge [combination of steps 630 and 640, adjust reading voltage by adding it to a constant voltage).
Regarding claim 2, Fig. 6 of Sivero discloses wherein the circuitry is configured to adjust the voltage [VPL] used to sense the data state of the memory cells of the group by: generating a first voltage signal having a constant voltage value [∆]; and generating a second voltage signal [VPL = VPL + ∆, also as shows in Fig. 5] that is a function of the determined amount of charge.
Regarding claim 3, Fig. 1 of Sivero discloses wherein: the circuitry includes a first capacitor [110] coupled to the first voltage signal [first voltage on PL] and a second capacitor [112] coupled to the second voltage signal [can be VPL or VPL+∆]; and the circuitry [120, 121, or 122] is configured to sense the data state of the memory cells of the group by: applying a voltage signal of the first capacitor to the voltage used to sense the data state [voltage on BL<0>] of the memory cells of the group; and applying a voltage signal of the second capacitor to the voltage used to sense the data state of the memory cells [voltage signal on BL<2>] while applying the voltage signal of the first capacitor to the voltage used to sense the data state of the memory cells.
Regarding claim 4, Fig. 1 of Sivero discloses wherein the circuitry includes an amplifier [AMP] configured to generate the first voltage signal [Vs].
Regarding claim 5, Fig. 3 of Sivero discloses wherein the circuitry [330] is configured to adjust the voltage used to sense the data state of the memory cells of the group by generating a single voltage signal [output of 330] that is a function of the determined amount of charge and a constant voltage value.
Regarding claim 6, Fig. 3 of Sivero discloses wherein: the circuitry includes a capacitor [315] coupled to the single voltage signal [315 couples to output of 330 through 320]; and the circuitry is configured to sense the data state of the memory cells of the group by applying a voltage signal of the capacitor [VS] to the voltage used to sense the data state of the memory cells.
Regarding claim 7, Fig. 1 and Fig. 2B of Sivero discloses the group of memory cells comprises a page of memory cells [each page connects to a big line, as shows in Fig. 2B]; and the sub-group comprises a portion of the memory cells [2 of 3 cells] of the page.
Regarding claim 8, Fig. 2A of Sivero discloses wherein the memory cells of the group are ferroelectric memory cells.
Regarding claim 9, Fig. 1 and Fig. 6 of Sivero discloses a method of operating memory, comprising:
determining an amount of charge [step 620, Fig. 6] associated with a sub-group of memory cells [110 and 112 in Fig. 1] of a memory, wherein:
the sub-group of memory cells [cells 110 and 112] comprise a portion [2 of 3 cells] of a group of memory cells of the memory; and
the sub-group of memory cells are always programmed to a same data state [both memory cells are programmed to sate “1”] throughout operation [a programming operation] of the memory;
adjusting a voltage [step 640] used to sense a data state of the memory cells of the group based, at least in part, on the determined amount of charge [base on step 630]; and
sensing the data state of the memory cells of the group using the adjusted voltage [step 650, Fig. 6].
Regarding claim 10, Fig. 1 of Sivero discloses wherein the sub-group of memory cells are programmed to a displacement polarization state [paragraphs 0016 and 0022].
Regarding claim 11, Fig. 2B of Sivero discloses wherein the method includes determining the amount of charge associated with the sub-group of memory cells by: applying a voltage [voltage on WL] to access lines [WL]of the sub-group of memory cells; and determining an amount of charge on data lines [BL, step 640, Fig. 6] of the sub-group of memory cells responsive to applying the voltage to the access lines [WL volage must be high in order to active a memory cell] of the sub-group of memory cells.
Regarding claim 12, Fig. 2B of Sivero discloses wherein the method includes sensing the data state of the memory cells of the group by: applying an additional voltage to access lines [another voltages applies to WL] of the group of memory cells after beginning to apply the voltage to the access lines of the sub-group of memory cells; and applying the adjusted voltage [VPL] to data lines [step 640, Fig. 6] of the group of memory cells while applying the additional voltage to the access lines of the group of memory cells [voltage on WL and PL and BL must be presented in order to select and sense a memory cell].
Regarding claim 13, Fig. 6 of Sivero discloses wherein the method includes determining the amount of charge [step 620] associated with the sub-group of memory cells responsive to receiving a command [read/sense command is inherent applied in order to perform a reading/sensing operation] to sense the data state of the memory cells of the group.
Regarding claim 14, Fig. 6 of Sivero discloses wherein the method includes: receiving an additional command [another read/sense command to perform another reading/sensing operation] to sense the data state of the memory cells of the group; determining an amount of charge [step 620] associated with the sub-group of memory cells responsive to receiving the additional command; adjusting the voltage [step 640] used to sense the data state of the memory cells of the group based, at least in part, on the amount of charge determined responsive to receiving the additional command; and sensing the data state of the memory cells of the group using the adjusted voltage [step 650].
Regarding claim 15, Fig. 1 and Fig. 6 of Sivero discloses an apparatus, comprising:
a memory having a group of memory cells [110 to 112, Fig. 1], wherein a sub-group of the memory cells [110 and 112] of the group are always programmed to a same average data state [both are programmed to state “1”] throughout operation [a program operation] of the memory; and
circuitry configured to:
determine an amount of charge [step 640 and 630 in Fig. 6] associated with the memory cells of the sub- group; and
adjust a voltage [step 640, adjust VPL] used to sense a data state of the memory cells of the group by adding a voltage value [∆] associated with the determined amount of charge to a constant voltage value [during calibration step in Fig. 3].
Regarding claim 16, Fig. 3 of Sivero discloses wherein the voltage value associated with the determined amount of charge is a function of the determined amount of charge [the amount of voltage change of VPL is depended on the amount of charge determined during reading operation, step 620 and 630s in Fig. 6].
Regarding claim 17, Fig. 3 of Sivero discloses wherein: the constant voltage value [∆] corresponds to a first voltage signal [Vs]; and the voltage value associated with the determined amount of charge corresponds to a second voltage signal [output of 330].
Regarding claim 18, Fig. 3 of Sivero discloses wherein the voltage value [VPL] associated with the determined amount of charge and the constant voltage value [∆] correspond to a single voltage signal [Vs].
Regarding claim 19, Fig. 3 of Sivero discloses wherein the circuitry [340] is configured to adjust the constant voltage value.
Regarding claim 20 Fig. 3 of Sivero discloses wherein the circuitry is configured to adjust the voltage [VPL] used to sense a data state [step 650, Fig. 6] of the memory cells of the group by no more than a particular amount [can be any amount].
Response to Arguments
Applicant's arguments filed 05/12/2026 have been fully considered but they are not persuasive.
Applicant argues that Sivero does not teach or suggest either alone or in combination wherein the sub-group of memory cells are always programmed to the same data state throughout operation of the memory. Applicant is reminded that the claims are examined in light of broadest reasonable. In addition, although the claims are examined in light of specification, limitations from specification are not read into the claims. As aforementioned and as shows the in Fig. 1, the sub-group of memory cells comprises cells 110 and 112. Also as discloses in paragraph 0020, both memory cells [110 and 112] are always programmed to the same data state [“1” throughout operation [programming operation] of the memory. Since applicant does not claim that the group of memory cells always programmed to the same state throughout all memory operations of the memory cell, any particular operation meets the claimed limitation. As discloses in paragraph 0020, the two memory cells are programmed to state “1” during a programming operation.
Therefore, all applicant’s arguments were fully considered, they are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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