DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "the highest state" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation "another state" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 10, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bathul et al. (US 20060152974 A1; hereinafter "Bathul").
Regarding claim 1, Bathul discloses a memory (para. [0001]), comprising: a memory array comprising a plurality of memory cells; and a peripheral circuit coupled with the memory array (claim 1: “A method of programming one or more memory bits on a wordline of a multi-level flash memory array, . . . “) and configured to: apply N program voltages to a word line coupled with a to-be-programmed memory cell with a target state to perform a first program operation (para. [0019]: “In the rough programming phase, . . . Programming continues until programming is done according to a predetermined Vd and Vg profile of successive programming pulses (e.g., about 50-200 mV step per program pulse of about 150 ns - 2 .mu.s pulse width) applied to the memory cells.”), to program the to-be-programmed memory cell to a first threshold voltage, wherein a difference between a target threshold voltage corresponding to the to-be-programmed memory cell with the target state and the first threshold voltage is less than a first preset value (para. [0056]: “As shown in FIG. 3, the rough threshold voltage value (e.g., Vr2, Vr3, Vr4) is offset (e.g., ∆2, ∆3, ∆4) some predetermined offset value (e.g., about 150-450 mV) less than the target threshold voltages Vt2, Vt3, and Vt4, respectively.”), and N is a positive integer; and apply M program voltages to the word line to perform a second program operation, to program both the to-be-programmed memory cell with the target state and other to-be-programmed memory cells that are coupled with the word line to respective corresponding target threshold voltages (para. [0020]: “Then in the fine programming phase, the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of successive programming pulses until the final target threshold voltage is achieved.”), wherein M is a positive integer.
Regarding claim 10, Bathul discloses a memory system, comprising: one or more memory, comprising: a memory array comprising a plurality of memory cells; and a peripheral circuit coupled with the memory array (claim 1: “A method of programming one or more memory bits on a wordline of a multi-level flash memory array, . . . “) and configured to: apply N program voltages to a word line coupled with a to-be-programmed memory cell with a target state to perform a first program operation (para. [0019]: “In the rough programming phase, . . . Programming continues until programming is done according to a predetermined Vd and Vg profile of successive programming pulses (e.g., about 50-200 mV step per program pulse of about 150 ns-2 .mu.s pulse width) applied to the memory cells.”), to program the to-be-programmed memory cell to a first threshold voltage, wherein a difference between a target threshold voltage corresponding to the to-be-programmed memory cell with the target state and the first threshold voltage is less than a first preset value (para. [0056]: “As shown in FIG. 3, the rough threshold voltage value (e.g., Vr2, Vr3, Vr4) is offset (e.g., ∆2, ∆3, ∆4) some predetermined offset value (e.g., about 150-450 mV) less than the target threshold voltages Vt2, Vt3, and Vt4, respectively.”), and N is a positive integer; and apply M program voltages to the word line to perform a second program operation, to program both the to-be-programmed memory cell with the target state and other to-be-programmed memory cells that are coupled with the word line to respective corresponding target threshold voltages (para. [0020]: “Then in the fine programming phase, the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of successive programming pulses until the final target threshold voltage is achieved.”), wherein M is a positive integer.
Regarding claim 11, Bathul discloses an operation method of a memory (claim 1: “A method of programming one or more memory bits on a wordline of a multi-level flash memory array, . . . “), comprising: applying N program voltages to a word line coupled with a to-be-programmed memory cell with a target state to perform a first program operation (para. [0019]: “In the rough programming phase, . . . Programming continues until programming is done according to a predetermined Vd and Vg profile of successive programming pulses (e.g., about 50-200 mV step per program pulse of about 150 ns-2 .mu.s pulse width) applied to the memory cells.”), to program the to-be-programmed memory cell to a first threshold voltage, wherein a difference between a target threshold voltage corresponding to the to-be-programmed memory cell with the target state and the first threshold voltage is less than a first preset value (para. [0056]: “As shown in FIG. 3, the rough threshold voltage value (e.g., Vr2, Vr3, Vr4) is offset (e.g., ∆2, ∆3, ∆4) some predetermined offset value (e.g., about 150-450 mV) less than the target threshold voltages Vt2, Vt3, and Vt4, respectively.”), and N is a positive integer; and applying M program voltages to the word line to perform a second program operation, to program both the to-be-programmed memory cell with the target state and other to-be-programmed memory cells that are coupled with the word line to respective corresponding target threshold voltages (para. [0020]: “Then in the fine programming phase, the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of successive programming pulses until the final target threshold voltage is achieved.”), wherein M is a positive integer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 4, 8, 9, 12, 14, 15, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bathul et al. (US 20060152974 A1; hereinafter "Bathul") in view of Park et al. (US 20210134359 A1; hereinafter "Park").
Regarding claims 2 and 12, Bathul teaches the memory and the operation method of the memory as set forth in the anticipation rejections of claims 1 and 11, respectively.
However, Bathul is silent with respect to a magnitude of each program voltage of the N program voltages applied during the first program operation is greater than magnitudes of at least some program voltages of the M program voltages applied during the second program operation.
Park, in the same field of endeavor, discloses “During the pre-program operation, a pre-program pulse Vpp may be applied to a word line coupled with memory cells selected as targets to be programmed. The pre-program pulse Vpp may be greater than the first program pulse Vp1.” (see FIG. 10 and para. [0096).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have designed the magnitude of the rough programming pulses (pre-programming pulses) of Bathul to be greater than magnitudes of at least some of the fine programming pulses (normal programming pulses), as taught by Park. One of ordinary skill in the art would have been motivated to make this modification for the benefit of removing holes present in boundaries between the memory cells corresponding to the upper program state and memory cells adjacent thereto (Park in para. [0094]).
Regarding claim 14, Bathul teaches the operation method of the memory as set forth in the anticipation rejections of claim 11.
However, Bathul does not teach acquiring a value of N, wherein the value of N is determined based on a test result of performing a program test on a test memory.
Park, in the same field of endeavor, teaches performing a pre-program operation that may include pre-programming memory cells to be programmed to an upper programmed state among the memory cells included in the selected physical page (para. [0007]). Performing programming testing on test memory is common in the art, and a person having ordinary skill in the art would have determined a number of programming pulses required to reach a preset or predetermined threshold voltage in a test memory cell by routine optimization. Bathul teaches a rough programming phase wherein the memory cells are to a rough threshold voltage and Park teaches a pre-program pulse that must be designed for the memory cells to reach an upper program state that is predetermined.
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to acquire a value of N, wherein the value of N is determined based on a test result of performing a program test on a test memory because it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Regarding claims 4 and 15, Bathul teaches the memory and the operation method of the memory as set forth in the anticipation rejections of claims 1 and 11, respectively.
However, Bathul does not teach a value of N is less than or equal to 2.
Park, in the same field of endeavor, discloses a pre-program pulse Vpp may be applied to a word line coupled with memory cells selected as targets to be programmed (see FIG. 10 and para. [0096) – thereby teaching N=1, which is less than 2.
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have designed the number of rough programming pulses (pre-programming pulses) of Bathul to be less than or equal to 2, as taught by Park. One of ordinary skill in the art would have been motivated to make this modification for the benefit of removing holes present in boundaries between the memory cells corresponding to the upper program state and memory cells adjacent thereto (Park in para. [0094]).
Regarding claims 8 and 19, Bathul teaches the memory and the operation method of the memory as set forth in the anticipation rejections of claims 1 and 11, respectively.
However, Bathul does not teach during the first program operation, apply a program permission voltage to a bit line coupled with the to-be-programmed memory cell with the target state, and apply a program prohibition voltage to a bit line coupled with the other to-be-programmed memory cells.
Park, in the same field of endeavor, discloses, “During the pre-program operation, a program enable voltage may be applied to each of bit lines coupled with memory cells to be pre-programmed among the selected memory cells, and program inhibit voltages may be applied to bit lines coupled with the other memory cells.” (Park at para. [0103).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have designed the first program operation to include applying a program permission voltage to a bit line coupled with the to-be-programmed memory cell with the target state, and applying a program prohibition voltage to a bit line coupled with the other to-be-programmed memory cells, as taught by Park. One of ordinary skill in the art would have been motivated to make this modification because it is a common practice in the art to enable the bit lines associated with memory cells to-be-programmed and to inhibit other bit lines (Official Notice).
Regarding claims 9 and 20, Bathul teaches the memory and the operation method of the memory as set forth in the anticipation rejections of claims 1 and 11, respectively.
However, Bathul does not teach during the second program operation, apply a program permission voltage to a bit line coupled with the to-be-programmed memory cell with the target state.
Park, in the same field of endeavor, discloses, “During the pre-program operation, a program enable voltage may be applied to each of bit lines coupled with memory cells to be pre-programmed among the selected memory cells, and program inhibit voltages may be applied to bit lines coupled with the other memory cells.” (Park at para. [0103). Park is silent with respect to the enable voltage during the normal program operation (second program operation), however, this is a common practice in the art and the normal program operation must also apply the same bit line voltage scheme.
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have designed the second program operation to include applying a program permission voltage to a bit line coupled with the to-be-programmed memory cell with the target state, as taught by Park. One of ordinary skill in the art would have been motivated to make this modification because it is a common practice in the art to enable the bit lines associated with memory cells to-be-programmed and to inhibit other bit lines (Official Notice).
Claim(s) 3, 5-7, 13, and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bathul et al. (US 20060152974 A1; hereinafter "Bathul") in view of Kim (US 20160203049 A1).
Regarding claims 3 and 13, Bathul teaches the memory and the operation method of the memory as set forth in the anticipation rejections of claims 1 and 11, respectively.
However, Bathul is silent with respect to during the first program operation, each time after a program voltage is applied to the word line, apply a verify voltage to the word line.
Kim, in the same field of endeavor, teaches a first programming operation using an incremental step pulse programming (ISPP) operation, wherein each of the program loops includes a program step of applying a program voltage to a selected word line and a verify step of applying a verify voltage to the selected word line, e.g., Vvfy11 (see Kim at FIG. 5 and para. [0069]).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have designed the rough programming phase of Bathul to include verification pulses after each programming pulse. One of ordinary skill in the art would have been motivated to make this modification for the benefit of verifying programming states of memory cells (see Kim at para. [0079]).
Regarding claims 5 and 16, Bathul teaches the memory and the operation method of the memory as set forth in the anticipation rejections of claims 1 and 11, respectively.
However, Bathul does not teach during the first program operation, apply a first program voltage to the word line; and after the first program voltage is applied during the first program operation, apply a second program voltage to the word line, wherein a magnitude of the first program voltage is less than a magnitude of the second program voltage.
Kim, in the same field of endeavor, teaches a first programming operation using an incremental step pulse programming (ISPP) operation, wherein as the program loops are performed, the program voltage increases sequentially (see Kim at FIG. 5 and para. [0069]).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have designed the rough programming phase of Bathul to include applying a second program voltage to the word line, wherein a magnitude of the first program voltage is less than a magnitude of the second program voltage, as taught by Kim. One of ordinary skill in the art would have been motivated to make this modification for the benefit of ensuring proper programming memory cells according to an ISPP scheme (Kim at para. [0069]).
Regarding claims 6 and 17, Bathul teaches the memory and the operation method of the memory as set forth in the anticipation rejections of claims 1 and 11, respectively.
However, Bathul does not teach a pulse width of each program voltage of the N program voltages is less than a pulse width of each program voltage of the M program voltages.
Kim, in the same field of endeavor, teaches a first programming operation and a second programming operation, wherein the program voltages of the first programming operation have a pulse with of a first time T1 and the program voltages of the second programming operation have a pulse width of a second T2. Kim discloses the second time T2 may be longer than the first time T1 (see Kim at FIG. 5 and para. [0078]).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have designed the rough programming pulses of Bathul to have pulse widths less than the fine programming pulse widths, as taught by Kim. One of ordinary skill in the art would have been motivated to make this modification for the benefit of providing a nonvolatile memory device with improved performance (Kim at para. [0072]).
Regarding claims 7 and 18, Bathul teaches the memory and the operation method of the memory as set forth in the anticipation rejections of claims 1 and 11, respectively.
However, Bathul does not teach during the second program operation, applying an initial program voltage to the word line; and performing the second program operation on the to-be-programmed memory cell with the target state and the other to-be-programmed memory cells coupled with the word line by gradually adding one step voltage increment based on the initial program voltage.
Kim, in the same field of endeavor, discloses the nonvolatile memory device 100 may perform the second program operation based on the ISPP scheme (para. [0078]) – which is well known in the art to include applying an initial program voltage to a word line and gradually adding one step voltage increments to the program voltage based on the initial program voltage.
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have designed the fine programming phase of Bathul to include an ISPP scheme, as taught by Kim. One of ordinary skill in the art would have been motivated to make this modification for the benefit of ensuring proper programming memory cells according to an ISPP scheme (Kim at para. [0069]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827
/HUAN HOANG/Primary Examiner, Art Unit 2827