DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19-20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the examiner is unable to determine how the second seal ring structure surrounds the second seal ring structure as required by claim 19.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims1-9 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen US Pub. No. 2022/0051993 in view of Chiu et al. US Pub. No. 2024/0038605 (Chiu).
In regards to Claim 1.
Chen discloses A method, comprising: forming an interconnect structure 250 over a front-side of a substrate 202 [0017-0024]; and forming a first seal ring structure 264 over the back-side of the substrate, wherein from a top view, the first seal ring structure [0025]
However Chen does not disclose, forming a power rail over a back-side of the substrate, wherein a footprint of the interconnect structure overlaps a footprint of the power rail on the substrate; and forming a first seal ring structure over the back-side of the substrate, wherein from a top view, the first seal ring structure surrounds the power rail.
Chiu teaches the formation of a power rail structure to the backside of a semiconductor structure [0026] (backside power rail).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a power rail formed over a back-side of the substrate as taught by Chiu in order to allow for increased gate density for greater device integration.
In regard to Claim 2, Chen discloses forming a second seal ring structure over the back-side of the substrate, wherein from the top view, the second seal ring structure 262 surrounds the first seal ring structure [0025].
In regards to Claim 3, Chen discloses forming a second seal ring structure over the front-side of the substrate, wherein from the top view, the second seal ring structure 262 surrounds the interconnect structure [0025].
In regards to Claim 4, Chen discloses wherein a footprint of the first seal ring structure overlaps a footprint of the second seal ring structure on the substrate [0025].
In regards to Claim 5, Chen discloses wherein a footprint of the first seal ring structure does not overlap a footprint of the second seal ring structure on the substrate [0025].
In regards to Claim 6, Chen wherein the first seal ring structure comprises: a back-side metal line having a ring-shaped top view profile; a plurality of first back-side vias landing on the back-side metal line and arranged in a first ring path; and a plurality of second back-side vias landing on the back-side metal line and arranged in a second ring path [0020-0028].
In regards to Claim 7, Chen wherein form the top view, the first back-side vias extend in a direction, and in the direction, adjacent two of the first and second back-side vias have a distance in a range from about 0.5 to 1.5 .u.m [0020-0028].
The examiner takes the position that the changes in dimension would not cause the claimed invention to perform differently from the prior art, (In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir 1984).
In regards to Claim 8, Chen wherein form the top view, the first back-side vias extend in a direction, and in the direction, adjacent two of the first and second back-side vias have a distance in a range from about 5 to 15 .u.m [0020-0028].
The examiner takes the position that the changes in dimension would not cause the claimed invention to perform differently from the prior art, (In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir 1984).
In regards to Claim 9, Chen discloses wherein the substrate comprises: a plurality of fin structures 250; and a plurality of epitaxial structures over the fin structures [0022].
In regards to Claim 11:
Chen discloses a method, comprising: forming a front-side metal layer over a front-side of a substrate, wherein from a top view, the front-side metal layer has a ring-shaped profile surrounding a circuit region of the substrate, and the front-side metal layer is a part of a front-side seal structure [0020-0028]; forming a plurality of first back-side metal vias over a back-side of the substrate, wherein from the top view, the first back-side metal vias are arranged in a ring path surrounding the circuit region of the substrate [0020-0028]; and forming a first back-side metal layer has a ring-shaped profile surrounding the circuit region of the substrate, and a footprint of the first back-side metal layer overlaps a footprint of the first back-side metal vias on the substrate [0020-0028].
In regards to Claim 12, Chen discloses wherein a footprint of the first back-side metal layer overlaps a footprint of the front-side metal layer [0020-0028].
In regards to Claim 13, Chen discloses forming a plurality of second back-side metal vias over the first back-side metal layer [0020-0028].
In regards to Claim 14, Chen discloses forming a second back-side metal layer over the second back-side metal vias, wherein from the top view, the second back-side metal layer has a ring-shaped profile surrounding the circuit region of the substrate [0020-0028].
In regards to Claim 15, Chiu discloses forming a power rail over the back-side of the substrate in the circuit region [0026].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a power rail formed over a back-side of the substrate in the circuit region as taught by Chiu in order to allow for increased gate density for greater device integration.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen US Pub. No. 2022/0051993 in view of Chiu et al. US Pub. No. 2024/0038605 (Chiu) as applied to claim 9 above, and further in view of Farooq et al. WO 2023/131505 A1 (Farooq).
Chen in view of Chiu teaches all the limitations of claim 10, however the combination does not teach: before forming the interconnect structure, forming a buried rail laterally between the fin structures from the front-side of the substrate, wherein after forming the first seal ring structure, the first seal ring structure is connected to the buried rail.
Farooq teaches a backside power rail 78 and back-side power delivery network (BSPDN) (ring-shaped). Backside ILD 76 abuts backside power rail 78. The power via 74 connects the backside power rail 78 to the BEOL interconnect layer 52 [0025].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to before forming the interconnect structure, forming a buried rail laterally between the fin structures from the front-side of the substrate, wherein after forming the first seal ring structure, the first seal ring structure is connected to the buried rail as taught by Farooq in order to efficiently and optimally power delivery to the backside network closest to the devices.
Claims 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen US Pub. No. 2022/0051993 in view of Chiu et al. US Pub. No. 2024/0038605 (Chiu) and Farooq et al. WO 2023/131505 A1 (Farooq).
In regards to Claim 16,
Chen discloses a substrate 202;
an interconnect structure 250 over a front-side of the substrate within a circuit region of the substrate [0017-0024];
a first seal ring structure 264 over the front-side of the substrate, wherein from a top view, the first seal ring structure surrounds the interconnect structure [0025];
Chen does not disclose a power rail over a back-side of the substrate within the circuit region of the substrate.
Chiu teaches the formation of a power rail structure to the backside of a semiconductor structure [0026] (backside power rail).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a power rail formed over a back-side of the substrate as taught by Chiu in order to allow for increased gate density for greater device integration.
Chen in view of Chiu does not disclose a second seal ring structure over the back-side of the substrate, wherein from the top view, the second seal ring structure surrounds the power rail.
Farooq teaches a backside power rail 78 and back-side power delivery network (BSPDN) (ring-shaped). Backside ILD 76 abuts backside power rail 78. The power via 74 connects the backside power rail 78 to the BEOL interconnect layer 52 [0025].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to before forming the interconnect structure, forming a buried rail laterally between the fin structures from the front-side of the substrate, wherein after forming the first seal ring structure, the first seal ring structure is connected to the buried rail as taught by Farooq in order to efficiently and optimally power delivery to the backside network closest to the devices.
In regards to Claim 17 Chen discloses wherein a footprint of the second seal ring structure overlaps a footprint of the first seal ring structure on the substrate [0020-0028].
Allowable Subject Matter
Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose the second ring and the power rail being the same height as required by claim 18, the forming a forth seal ring on the backside that surrounds a third seal ring as required by claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WALTER LEE LINDSAY JR whose telephone number is (571)272-1674. The examiner can normally be reached Monday-Thursday 9-7.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allana Lewin Bidder can be reached at 571-272-5560. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WALTER L LINDSAY JR/Supervisory Patent Examiner, Art Unit 2852
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