DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2 recites “a gate region” in line 2 while claim 1 already recited “a gate electrode” in line 7. It is unclear to the examiner if the gate region is another gate electrode or the same gate electrode in line 7 of claim 1.
Claim 18 recites the limitation “the etched oxide film”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 6, 12 and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (Pub. No.: US 2022/0310839 A1), hereinafter as Yang.
Regarding claim 1, Yang discloses a high voltage semiconductor device in Fig. 1, comprising: a substrate (substrate 10) (see [0019]); a drift region (region 26) disposed on a surface side of the substrate within the substrate (see [0024]); a body region (region 25) disposed on the surface side of the substrate within the substrate (see [0024]); a drain region (drain 52D) disposed within the drift region (see [0019]); a source region (source 52S) disposed within the body region (see [0019]); a gate electrode (gate GS1) disposed on the substrate between the source region and the drain region (see [0028]); a gate field plate (oxide layer 40) disposed on a bottom side of the gate electrode on a substrate surface (see [0028]); an insulating pattern (oxide layer 60) disposed on the gate electrode and the gate field plate (see [0028]); and a field plate (field plate 70) disposed on the insulating pattern (see [0028]).
Regarding claim 5, Yang discloses the high voltage semiconductor device of claim 1, wherein the insulating pattern has a width size (length measuring in Fig. 1) substantially equal to a width size of the field plate (see Fig. 1).
Regarding claim 6, Yang discloses the high voltage semiconductor device of claim 5, wherein the field plate is formed with the insulating pattern in a single etching process (concurrently by the same patterning) (see [0022]).
Furthermore, it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 6 is directed to a device, the method of forming the field plate and the insulating pattern is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…in a single etching process” stated in claim 6 has not been given any patentable weight. MPEP 2113 [R-1].
Regarding claim 12, Yang discloses a high voltage semiconductor device in Fig. 1, comprising: a substrate (substrate 10) (see [0019]); a drift region (region 26) disposed on a surface side of the substrate within the substrate (see [0024]); a body region (region 25) disposed on the surface side of the substrate within the substrate (see [0024]); a gate electrode (gate GS1) disposed on the substrate between the source region and the drain region (see [0028]); a buried layer (region 21) disposed below the drift region within the substrate (see [0024]); a lower well region (region 22) disposed between the drift region and the buried layer (see [0024]); a gate field plate (oxide layer 40) disposed on a bottom side of the gate electrode on a surface side of the drift region (see [0028]; an insulating pattern (oxide layer 60) disposed on the gate electrode and the gate field plate (see [0028]); and a field plate (field plate 70) disposed on the insulating pattern (see [0028]) and having a width size substantially equal to a width size (length measuring in Fig. 1) of the insulating pattern.
Regarding claim 13, Yang discloses the high voltage semiconductor device of claim 12, wherein the drift region has an impurity doped region of a second conductivity type (n type) and the lower well region has an impurity doped region of a first conductivity type (region 22 having p type) (see [0024]).
Regarding claim 14, Yang discloses the high voltage semiconductor device of claim 12, wherein the insulating pattern and the field plate are formed using a single mask pattern. (concurrently by the same patterning) (see [0022]).
Furthermore, it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 14 is directed to a device, the method of forming the field plate and the insulating pattern is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…are formed using a single mask pattern” stated in claim 14 has not been given any patentable weight. MPEP 2113 [R-1].
Regarding claim 15, Yang discloses the high voltage semiconductor device of claim 14, wherein one end of the field plate and one end of the insulating pattern are disposed on a same vertical plane, and another opposite end of the field plate and another opposite end of the insulating pattern are disposed on another same vertical plane.
Regarding claim 16, Yang discloses a method of manufacturing a high voltage semiconductor device in Fig. 1, the method comprising: forming a drift region (region 26) on a surface of a substrate (substrate 10) within the substrate (see [0019] and [0024]); forming a body region (region 25) on the surface of the substrate within the substrate (see [0024]); forming a gate field plate (oxide layer 40) on the surface of the substrate on a drift region side (see [0028]; forming a gate region (gate GS1) on the surface of the substrate (see [0028]); and forming an insulating pattern (oxide layer 60) and a field plate (field plate 70) on the gate region and the gate filed plate (see [0028]).
Regarding claim 17, Yang discloses the method of claim 16, wherein the forming the insulating pattern and the field plate comprises: forming an insulating layer (forming silicon oxide layer) on the substrate to cover the gate region and the gate field plate; forming a polysilicon film (forming doped polysilicon) on the insulating layer; forming a mask pattern (a mask from patterning process) on the polysilicon film; and etching the polysilicon film and the insulating layer together using the mask pattern (formed concurrently by the same patterning process) (see Fig. 1 and [0022]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (Pub. No.: US 2022/0310839 A1), hereinafter as Yang, as applied to claim 1 and in view of Takehiro (Pub No.: 2010/0181616 A1).
Regarding claim 2, Yang discloses the high voltage semiconductor device of claim 1, fails to disclose wherein the gate field plate has a thickness less than half a thickness of a gate region.
Takehiro discloses a high voltage semiconductor device in Fig. 14A comprising wherein a gate field plate (oxide film 40 has 40 nm) has a thickness less than half a thickness of a gate region (gate electrode 50 has 100 nm) (see [0079-0080]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the thickness of the gate field plate of Yang to be less than half the thickness of gate region because the modified structure would enhance break down voltage for semiconductor device.
Regarding claim 3, Yang discloses the high voltage semiconductor device of claim 1, fails to disclose wherein the gate field plate has a thickness range of 300 Å or more and 1200 Å or less.
Takehiro discloses a high voltage semiconductor device in Fig. 14A comprising wherein the gate field plate has a thickness range of 300 Å or more and 1200 Å or less (oxide film 40 has 40-1000 nm) (see [0079-0080]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the thickness of the gate field plate of Yang to be less than half the thickness of gate region because the modified structure would enhance break down voltage for semiconductor device.
Regarding claim 4, Yang discloses the high voltage semiconductor device of claim 1, fails to disclose wherein the gate field plate has a thickness range of 800 Å or more and 1000 Å or less.
Takehiro discloses a high voltage semiconductor device in Fig. 14A comprising wherein the gate field plate has a thickness range of 300 Å or more and 1200 Å or less (oxide film 40 has 40-1000 nm) (see [0079-0080]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the thickness of the gate field plate of Yang to be less than half the thickness of gate region because the modified structure would enhance break down voltage for semiconductor device.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (Pub. No.: US 2022/0310839 A1), hereinafter as Yang, as applied to claim 5.
Regarding claim 7, Yang discloses the high voltage semiconductor device of claim 5, but fails to disclose wherein a width size of a portion of the insulating pattern in contact with the gate field plate has a range of 50% or more and 70% or less of the width size of the insulating pattern.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein a width size of a portion of the insulating pattern in contact with the gate field plate has a range of 50% or more and 70% or less of the width size of the insulating pattern because it would improve the device functionality by reducing leakage and parasitic capacitance. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 8, Yang discloses the high voltage semiconductor device of claim 5, but fails to disclose wherein the insulating pattern has a thickness ratio within a range of 1 times or more and 1.2 times or less compared to the gate field plate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein the insulating pattern has a thickness ratio within a range of 1 times or more and 1.2 times or less compared to the gate field plate because it would improve the device functionality by reducing leakage and parasitic capacitance. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 9, Yang discloses the high voltage semiconductor device of claim 5, but fails to disclose wherein the gate field plate has a thickness ratio within a range of 0.2 times or more and 0.3 times or less compared to the gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein the gate field plate has a thickness ratio within a range of 0.2 times or more and 0.3 times or less compared to the gate electrode because it would improve the device functionality by improve breakdown voltage and reducing leakage. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (Pub. No.: US 2022/0310839 A1), hereinafter as Yang, as applied to claim 1 and in view of Miller, JR. et al. (Pub No.: 2007/0018273 A1), hereinafter as Miller JR.
Regarding claim 10, Yang discloses the high voltage semiconductor device of claim 1, fails to disclose further comprising: an LDD region disposed within the body region.
Miller JR. discloses a high voltage semiconductor device in Fig. 2P comprising an LDD region (implant 208) disposed within a body region (P-well 207) (see [0018] and [0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the LDD region of Miller JR. into the high voltage semiconductor device of Yang because the modified structure would provide a high-performance semiconductor device by reducing hot carrier effect and suppressing short channel effect.
Regarding claim 11, the combination of Yang and Miller JR. discloses the high voltage semiconductor device of claim 10, wherein the LDD region has a shallower depth from the substrate surface within the substrate than a depth of the source region (depth of implant 208 is shallower than the depth of source 267) (see Miller JR., and Fig. 2P).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (Pub. No.: US 2022/0310839 A1), hereinafter as Yang, as applied to claim 16 and in view of Bauer et al. (Pub No.: 2025/0006836 A1), hereinafter as Bauer.
Regarding claim 18, Yang discloses the method of claim 16, but fails to disclose wherein the forming the gate field plate comprises: forming a pad oxide film on the substrate; forming a nitride film on the pad oxide film; forming a mask pattern on the nitride film; sequentially etching the nitride film, the pad oxide film, and the surface of the substrate; and growing the etched oxide film through a thermal oxidation process.
Bauer discloses a method of manufacturing a high voltage semiconductor device comprising: forming a gate field plate (dielectric layer 126) comprises: forming a pad oxide film (pad oxide layer 110) on the substrate (see Fig. 1A and [0019]); forming a nitride film (silicon nitride layer 112) on the pad oxide film (see Fig. 1A and [0019]); forming a mask pattern (photomask not shown) on the nitride film (see [0019]); sequentially etching the nitride film, the pad oxide film, and the surface of a substrate (substrate 103) (etching layer 110 and 112, will likely etched into substrate 103 to form opening 122) (see Fig. 1B and [0020]); and growing the etched oxide film (growing dielectric layer 126) through a thermal oxidation process (by LOCOS furnace oxidation 124) (see Fig. 1B and [0020]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the method of forming gate field plate of Bauer into the method of Yang using pad oxide film, silicon nitride film, mask pattern and thermal oxidation process because the modified method would provide a reliable and low cost manufacturing for creating the gate field plate for the high voltage semiconductor device.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (Pub. No.: US 2022/0310839 A1), hereinafter as Yang, as applied to claim 16 and in view of Matsuda (Pub No.: 2015/0295081 A1).
Regarding claim 19, Yang discloses the method of claim 16, forming a drain region (drain 52D) and forming a source region (source 52S) within the body region (see Fig. 1 and [0019]). But Yang fails to disclose forming a drain extension region within the drift region so that the drain region within the drain extension region.
Matsuda, discloses a method of manufacturing a high voltage semiconductor device in Figs. 9, 10A-12 comprising forming a drift region (drift 21) (see Figs. 9, 10A and [0110]), forming a drain extension region (drift 22) within the drift region (see Figs. 9, 10A and [0110]); forming a drain region (drain 9) within the drain extension region (see Fig. 11C and [0112]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the method of forming the drain extension region within the drift region of Matsuda into the method of Yang because the modified method would provide a high-performance device with higher breakdown voltage.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (Pub. No.: US 2022/0310839 A1), hereinafter as Yang in view of Matsuda (Pub No.: 2015/029508 A1), as applied to claim 19 and further in view of Miller, JR. et al. (Pub No.: 2010/0181616 A1), hereinafter as Miller JR.
Regarding claim 20, the combination of Yang and Matsuda discloses the method of claim 19, but fails to disclose forming an LDD region within the body region before forming the source region.
Miller JR. discloses a method of manufacturing a high voltage semiconductor device in Fig. 2P comprising forming an LDD region (implant 208) disposed within a body region (P-well 207) before forming a source region (implant 267) (see [0018] and [0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the metho of forming the LDD region of Miller JR. into the high voltage semiconductor device of Yang before forming the source region because the modified method would provide a high-performance semiconductor device by reducing hot carrier effect and suppressing short channel effect.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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