DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/13/24 & 08/29/24 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Claim Objections
Claims 17-20 are objected to because of the following informalities: claim 17 should recite “…transistor of the second memory cell… transistor of the third memory cell…” instead of “…transistor of second memory cell… transistor of third memory cell…”. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 31-34 of U.S. Patent No. 11,985,806. Although the claims at issue are not identical, they are not patentably distinct from each other because: (1) independent claim 17 of this application and independent claim 30 of patent ‘806 are substantially identical (see table below) except for the positional expressions “adjacent” (claim 17) and “located over” (claim 31), and the substrate recited in claim 31, wherein it would have been obvious to one skilled in the art to have provided the conductive region of claim 17 over a substrate (such as a semiconductor substrate) as a non-inventive step of forming a memory-based apparatus as conventionally done in the art, and also provided any structure adjacent to another one to be located over the said another one as a non-inventive design choice as desired or required for a given device performance; (2) claims 18, 19 and 20 of this application are the same as respectively claims 32, 33 and 34 of patent ‘806.
Application 18/662,659
Patent 11,985,806
17. An apparatus comprising: a conductive region; a first memory cell adjacent the conductive region, the fist memory cell including a first transistor and a second transistor adjacent the first transistor; a second memory cell adjacent the conductive region, the second memory cell including a first transistor and a second transistor located adjacent the first transistor of second memory cell; a third memory cell adjacent the conductive region, the third memory cell including a first transistor a second transistor adjacent the first transistor of third memory cell; a first conductive structure between the first and second memory cells, the first conductive structure contacting the conductive region; and a second conductive structure between the second and third memory cells, the second conductive structure contacting the conductive region.
18. The apparatus of claim 17, wherein each of the first, second, and third memory cells includes a memory element, and wherein: the first conductive structure is between the memory element of the first memory cell and the memory element of the second memory cell; and the second conductive structure is between the memory element of the second memory cell and the memory element of the third memory cell.
19. The apparatus of claim 17, wherein the second transistors of each of the first, second, and third memory cells includes a channel region coupled to the memory element of a respective memory cell of the first, second, and third memory cells.
20. The apparatus of claim 19, wherein the first transistors of each of the first, second, and third memory cells includes a channel region, and the memory element of each of the first, second, and third memory cells includes: a first portion adjacent a first side of the channel region of a respective memory cell of the first, second, and third memory cells, and a second portion adjacent a second side of the channel region of a respective memory cell of the first, second, and third memory cells.
31. An apparatus comprising: a conductive region over substrate; a first memory cell located over the conductive region, the first memory cell including a first transistor and a second transistor located over the first transistor; a second memory cell located over the conductive region, the second memory cell including a first transistor and a second transistor located over the first transistor of second memory cell; a third memory cell located over the conductive region, the third memory cell including a first transistor a second transistor located over the first transistor of third memory cell; a first conductive structure between the first and second memory cells, the first conductive structure contacting the conductive region; and a second conductive structure between the second and third memory cells, the second conductive structure contacting the conductive region.
32. The apparatus of claim 31, wherein each of the first, second, and third memory cells includes a memory element, and wherein: the first conductive structure is between the memory element of the first memory cell and the memory element of the second memory cell; and the second conductive structure is between the memory element of the second memory cell and the memory element of the third memory cell.
33. The apparatus of claim 31, wherein the second transistors of each of the first, second, and third memory cells includes a channel region coupled to the memory element of a respective memory cell of the first, second, and third memory cells.
34. The apparatus of claim 33, wherein the first transistors of each of the first, second, and third memory cells includes a channel region, and the memory element of each of the first, second, and third memory cells includes: a first portion adjacent a first side of the channel region of a respective memory cell of the first, second, and third memory cells, and a second portion adjacent a second side of the channel region of a respective memory cell of the first, second, and third memory cells.
Allowable Subject Matter
Claims 1-16 are allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kalnitsky et al. (US 8,320,180; US 8,218,370), Bhattacharyya et al. (US 2006/0044870) and Caywood (US 6,201,732) disclose structures similar to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899
Prosecution Insights