DETAILED ACTION
This correspondence is in response to the communications received April 21, 2026. Claims 1-12 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claim 1-12) in the reply filed on June 15, 2026 is acknowledged.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Figs. 16-18, a semiconductor structure comprising:
a semiconductor substrate (“P type Silicon Substrate ( or P well)”);
a first dielectric layer (“gate dielectric layer 331”, ¶ 0098) directly on a first portion of the semiconductor substrate (partial upper surface location of 331 on the substrate),
wherein a length of the first dielectric layer is the same as that of the first portion of the semiconductor substrate (In an interpretation, this could just be where the 331 makes contact with substrate is the same length); and
an undoped semiconductor layer (“a thin layer (such as 6~10nm) of undoped or doped amorphous silicon (or polysilicon) 3321 is first deposited at temperature of 500~650℃ over the gate dielectric layer 331”, ¶ 0098) on the first dielectric layer (3321 on 331).
Regarding claim 9, the Applicant discloses in Figs. 16-18, a semiconductor structure comprising:
a semiconductor substrate (“P type Silicon Substrate ( or P well)”);
a first dielectric layer (“gate dielectric layer 331”, ¶ 0098) directly on a first portion of the semiconductor substrate (partial upper surface location of 331 on the substrate),
wherein a length of the first dielectric layer is the same as that of the first portion of the semiconductor substrate (In an interpretation, this could just be where the 331 makes contact with substrate is the same length);
a first semiconductor layer (“a thin layer (such as 6~10nm) of undoped or doped amorphous silicon (or polysilicon) 3321 is first deposited at temperature of 500~650℃ over the gate dielectric layer 331”, ¶ 0098) on the first dielectric layer (3321 on 331);
wherein the first semiconductor layer includes a first Si containing material (¶ 0098), and a size of a grain in the first Si containing material is greater than 1um (“Then, such amorphous silicon layer is annealed at temperature around 1000℃ or higher (such as, laser annealing ~1200C plus thermal annealing ~600C ) for recrystallization and turned into larger grains silicon layer, and the size of the grain could be more than 1~2um”, ¶ 0098 and also stated as disclosed support in ¶ 0099); and
a dielectric cap layer over the first semiconductor layer (Not shown in the drawings for this configuration, but as this claim is originally filed, it at least has support in the filing date of this application. The concept of a dielectric cap on a semiconductor gate being a typical feature known in the art.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chong et al. (US 2007/0132038) in view of Cunningham (US 6,208,004).
The filing date of this Application 18/662,717, is May 13, 2024. However, this is not the effective date of the Application.
Application 18/203,688 (May 31, 2023) does not have any support for crystal grain size nor undoped gate electrode aspects.
Provisional Application 63/348,050 (June 2, 2022) does not have any support for crystal grain size nor undoped gate electrode aspects.
Both Provisional Application 63/618,930 and Application 18/422,360 appear to support aspects of crystal grain size and undoped gate electrode.
This analysis has established that the effective date is January 9, 2024.
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Regarding claim 1, the prior art of Chong discloses in Fig. 1, a semiconductor structure (“This invention relates generally to devices and methods for the fabrication of semiconductor devices and more particularly to the fabrication of FET's having embedded Source/Drain regions.”, ¶ 0002, wherein the ‘structure’ can be the transistor (e.g. FET) formed in the substrate) comprising:
a semiconductor substrate (“Si substrate 10”, ¶ 0062, where ‘Si’ signifies silicon, which is a semiconductor material);
a first dielectric layer (“gate dielectric 32”, ¶ 0024, or “gate dielectric 30”, ¶ 0029) directly on a first portion of the semiconductor substrate (This is interpreted as, the portion of upper surface of 10 which directly meets where 30 or 32 interfaces therewith, hereinafter referred to as ‘FPSS’. Further, this claim limitation is interpreted in light of what Applicant discloses in their disclosure, which is similarly arranged as interpreted against the Chong reference.),
wherein a length of the first dielectric layer is the same as that of the first portion of the semiconductor substrate (The portion of the substrate FPSS that meets the gate dielectric 30 is the same length. It is noted that the “length” associated with a transistor is the dimension of distance between the source and drain, which is the gate dimension, the gate dielectric immediately under the gate, and is also the channel length); and
a semiconductor layer (either of “gate 36 can be comprised of poly-Si”, ¶ 0024, or “the PFET poly-Si gate”, ¶ 0067, which is 34) on the first dielectric layer (either of 36 or 34 on 32 or 30).
Chong does not disclose the particular method steps of the formation of the poly gate, and therefore does not disclose, “an undoped semiconductor layer on the first dielectric layer.”
Cunningham discloses in col. 8, lines 9-11, “The dopants would then penetrate the films lying over the undoped polysilicon forming the appropriate p+ and n+ polysilicon gate electrodes”. So Cunningham discloses that prior to the doping of the poly gate layer, which is when the poly gate becomes conductive so as to be a functional conductor, so it can function as a gate electrode. There is an initial period of time, where the polysilicon layer is undoped as it is deposited and formed into a semiconductor, prior to it’s doping step.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “an undoped semiconductor layer on the first dielectric layer”, as disclosed by Cunningham in the system of Chong, for the purpose of forming the semiconductor material which will ultimately be transformed into a functionally conductive gate electrode which will allow for the basic function of the transistor device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Chong et al. disclose the semiconductor structure in claim 1, wherein a first sidewall (one of the left or right sidewalls of 36 or 34) of the undoped semiconductor layer (Chong’s Fig. 1, elements 36 or 34 prior to doping as addressed in the rejection of claim 1) is covered by a second dielectric layer (“spacers 44 can be comprised of thermal oxide”, ¶ 0026, and “spacers 42”, ¶ 0029), and a second sidewall (other one of the left or right sidewalls of 36 or 34) of the undoped semiconductor layer (Chong’s Fig. 1, elements 36 or 34 prior to doping as addressed in the rejection of claim 1) opposite to the first sidewall is covered by a third dielectric layer (other side covered by further segments of, “spacers 44 can be comprised of thermal oxide”, ¶ 0026, and “spacers 42”, ¶ 0029).
Regarding claim 3, the prior art of Chong et al. disclose the semiconductor structure in claim 2, wherein the undoped semiconductor layer includes a Si containing material (either of “gate 36 can be comprised of poly-Si”, ¶ 0024, or “the PFET poly-Si gate”, ¶ 0067, which is 34).
Regarding claim 5, the prior art of Chong et al. disclose the semiconductor structure in claim 2, wherein the first dielectric layer includes oxide (Chong Fig. 1, shows wherein “spacers 44 can be comprised of thermal oxide”, ¶ 0026).
Regarding claim 6, the prior art of Chong et al. disclose the semiconductor structure in claim 3, wherein both the second dielectric layer and third dielectric layer include oxide (Chong Fig. 1, shows wherein “spacers 44 can be comprised of thermal oxide”, ¶ 0026).
Regarding claim 7, the prior art of Chong et al. disclose the semiconductor structure in claim 2, further comprising a dielectric cap layer over the undoped semiconductor layer (Chong shows in Fig. 1, where a gate cap 40, ¶ 0025, “gate capping layer 40 can be comprised of nitride or SiOXNY or SiO2”, formed over poly gate 36, ¶ 0024).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chong et al. (US 2007/0132038) in view of Ishida (JP H05198795 A).
Regarding claim 9, the prior art of Chong discloses in Fig. 1, a semiconductor structure (“This invention relates generally to devices and methods for the fabrication of semiconductor devices and more particularly to the fabrication of FET's having embedded Source/Drain regions.”, ¶ 0002, wherein the ‘structure’ can be the transistor (e.g. FET) formed in the substrate) comprising:
a semiconductor substrate (“Si substrate 10”, ¶ 0062, where ‘Si’ signifies silicon, which is a semiconductor material);
a first dielectric layer (“gate dielectric 32”, ¶ 0024, or “gate dielectric 30”, ¶ 0029, materials listed in ¶ 0024) directly on a first portion of the semiconductor substrate (This is interpreted as, the portion of upper surface of 10 which directly meets where 30 or 32 interfaces therewith, hereinafter referred to as ‘FPSS’. Further, this claim limitation is interpreted in light of what Applicant discloses in their disclosure, which is similarly arranged as interpreted against the Chong reference.),
wherein a length of the first dielectric layer is the same as that of the first portion of the semiconductor substrate (The portion of the substrate FPSS that meets the gate dielectric 30 is the same length. It is noted that the “length” associated with a transistor is the dimension of distance between the source and drain, which is the gate dimension, the gate dielectric immediately under the gate, and is also the channel length); and
a first semiconductor layer (either of “gate 36 can be comprised of poly-Si”, ¶ 0024, or “the PFET poly-Si gate”, ¶ 0067, which is 34) on the first dielectric layer (either of 36 or 34 on 32 or 30).
wherein the first semiconductor layer includes a first Si containing material (either of “gate 36 can be comprised of poly-Si”, ¶ 0024, or “the PFET poly-Si gate”, ¶ 0067, which is 34),
a dielectric cap layer (either of, “gate capping layer 40 can be comprised of nitride or SiOXNY or SiO2”, ¶ 0025, or, “PFET gate capping layer 38 and NFET gate capping layer 40”, ¶ 0053, where 38 being a ‘gate capping layer’ is understood to be of the same material as that of 40.) over the first semiconductor layer (over 34 or 36).
Chong does not specify, “wherein the first semiconductor layer includes … a size of a grain in the first Si containing material is greater than 1um”.
Ishida discloses, in title, “POLY-SI GATE ELECTRODE FOR MIS-TYPE SEMICONDUCTOR ELEMENT”, and abstract, “PURPOSE: To provide a gate electrode to suppress the variation of characteristics of an element due to the diffusion of boron from a P(+) Poly-Si gate electrode and at the same time to achieve the low-resistance of the gate electrode itself and manufacture thereof. CONSTITUTION: In a boron-doped poly-Si gate electrode for an MIS-type semiconductor element, there are provided a poly-Si gate electrode and manufacture thereof, wherein the crystal grain diameter of poly-Si in which boron is doped is at least 0.3mum or more.”, and ¶ 0004, “According to the present invention, when PolySi is used as a gate electrode of a MOS transistor, the larger the crystal grain of PolySi is, the higher the crystal grain size is, the higher the activation rate of doped impurities is. Focusing on the effect of improvement, the object of the present invention can be achieved by satisfying the following basic configuration. By increasing the crystal grain size of PolySi, the resistance of the gate electrode can be lowered even if the doping concentration is low, and the amount of boron diffused due to this low concentration can be reduced. The range of suitable conditions such as the crystal grain size of PolySi, the doping concentration, the activation temperature, and the film thickness of the gate insulating film changes in relation to other conditions, but the PolySi crystal grain size is shown in FIG. As is clear from the description, at least 0.3 μm or more is required. If PolySi having a grain size of 0.3 μm or more is used, the doping concentration is at most 3 × 10 .sup.19 atoms / cm .sup.2.”
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the first semiconductor layer includes … a size of a grain in the first Si containing material is greater than 1um”, as disclosed by Ishida in the system of Chong, for the purpose of forming a polysilicon gate electrode which lowers gate resistance, which allows for a higher performing device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 10, the prior art of Chong et al. disclose the semiconductor structure in claim 9, wherein a first sidewall (one of the left or right sidewalls of 36 or 34) of the first semiconductor layer (Chong’s Fig. 1, elements 36 or 34 which are interpreted to be the “first semiconductor structure” are addressed in the rejection of claim 1) is covered by a second dielectric layer (“spacers 44 can be comprised of thermal oxide”, ¶ 0026, and “spacers 42”, ¶ 0029), and a second sidewall (other one of the left or right sidewalls of 36 or 34) of the undoped semiconductor layer (Chong’s Fig. 1, elements 36 or 34 which are interpreted to be the “first semiconductor structure” are addressed in the rejection of claim 1)opposite to the first sidewall is covered by a third dielectric layer (other side covered by further segments of, “spacers 44 can be comprised of thermal oxide”, ¶ 0026, and “spacers 42”, ¶ 0029).
Regarding claim 11, the prior art of Chong et al. disclose the semiconductor structure in claim 10, wherein the first dielectric layer includes oxide (“gate dielectric 32 can be comprised of SiOXNY, nitrided SiO2 (either by plasma or thermal means, or a combination thereof), HfO2, HfSiXOY, HfAlXOY”, ¶ 0024), and both the second dielectric layer and third dielectric layer include oxide (both sides of the spacers, “spacers 44 can be comprised of thermal oxide”, ¶ 0026, and “spacers 42”, ¶ 0029).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chong et al. (US 2007/0132038) in view of Cunningham (US 6,208,004) in view of Ishida (JP H05198795 A).
Regarding claim 4, the prior art of Chong et al. disclose the semiconductor structure in claim 3, however Chong does not disclose, “wherein a size of a grain in the Si containing material is greater than 1um.”
Ishida discloses, in title, “POLY-SI GATE ELECTRODE FOR MIS-TYPE SEMICONDUCTOR ELEMENT”, and abstract, “PURPOSE: To provide a gate electrode to suppress the variation of characteristics of an element due to the diffusion of boron from a P(+) Poly-Si gate electrode and at the same time to achieve the low-resistance of the gate electrode itself and manufacture thereof. CONSTITUTION: In a boron-doped poly-Si gate electrode for an MIS-type semiconductor element, there are provided a poly-Si gate electrode and manufacture thereof, wherein the crystal grain diameter of poly-Si in which boron is doped is at least 0.3mum or more.”, and ¶ 0004, “According to the present invention, when PolySi is used as a gate electrode of a MOS transistor, the larger the crystal grain of PolySi is, the higher the crystal grain size is, the higher the activation rate of doped impurities is. Focusing on the effect of improvement, the object of the present invention can be achieved by satisfying the following basic configuration. By increasing the crystal grain size of PolySi, the resistance of the gate electrode can be lowered even if the doping concentration is low, and the amount of boron diffused due to this low concentration can be reduced. The range of suitable conditions such as the crystal grain size of PolySi, the doping concentration, the activation temperature, and the film thickness of the gate insulating film changes in relation to other conditions, but the PolySi crystal grain size is shown in FIG. As is clear from the description, at least 0.3 μm or more is required. If PolySi having a grain size of 0.3 μm or more is used, the doping concentration is at most 3 × 10 .sup.19 atoms / cm .sup.2.”
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein a size of a grain in the Si containing material is greater than 1um”, as disclosed by Ishida in the system of Chong, for the purpose of forming a polysilicon gate electrode which lowers gate resistance, which allows for a higher performing device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Allowable Subject Matter
Claims 8 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 8, the prior art of Chong et al. (US 2007/0132038) in view of Cunningham (US 6,208,004) in view of Ishida (JP H05198795 A) fail to disclose the features set forth claim 8, which include a second semiconductor layer in the gate region, which further includes a larger grain size, “further comprising a doped semiconductor layer between the dielectric cap layer and the undoped semiconductor layer … and a size of a grain in the Si containing material is greater than 1um.”
Regarding claim 12, the prior art of Chong et al. (US 2007/0132038) in view of Cunningham (US 6,208,004) in view of Ishida (JP H05198795 A) fail to disclose the features set forth claim 12, which include a second semiconductor layer in the gate region, which further includes a larger grain size, “further comprising a second semiconductor layer between the dielectric cap layer and the first semiconductor layer … and a size of a grain in the second Si containing material is greater than 1um.”
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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