DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, and 4-14, is/are rejected under 35 U.S.C. 103 as being unpatentable over U. S. Patent Application Publication No. 2013/0260313 (hereinafter referred to as Allen) in view of U. S. Patent Application Publication No. 2003/0117598 (hereinafter referred to as Case) and U. S. Patent Application Publication No. 2010/0240555 (hereinafter referred to as Sundararajan).
Allen, in [0003], [0166], [0180] and [0117], discloses using photoresist in the manufacture of semiconductor devices (electronic parts or circuit boards etc.,) and the process including using a substrate that includes a layered structure of a semiconductor device (the claimed device layer) and that the substrate surface can include a metal layer. Allen, in [0174], [0168], discloses that prior to coating photoresist, the substrate (device) is primed with HMDS (silylation, promoter layer) i.e., the substrate with a device layer is vapor primed with HMDS, and includes baking (first baking) after priming the substrate with the HMDS. Allen, in [0167]-[0169], discloses coating a photoresist layer on a primed substrate, and Allen, in [0169], discloses that the coated photoresist is subjected to a post-application bake (claimed second baking process) at about 80°C to about 130°C for a period of greater than 10 seconds to less than 120 seconds. Allen, in [0172], teaches pattern-wise exposing the photoresist layer using a mask (photomask) to a radiation in the claimed wavelength (365nm). Allen, in [0099], discloses that the exposed photoresist is subjected to development, and Allen, in [0114], discloses that a post-development thermal treatment (claimed third baking process) is performed on the developed photoresist (patterned photoresist layer), wherein the post-development thermal treatment is conducted at a temperature range of greater than 50°C and less than 200°C for a duration of greater than 1 second (includes 35-65 seconds) (claims 1, and 6-10). Allen, in [0176]-[0179], discloses that the patterned photoresist layer is formed after developing the exposed photoresist layer and that only the photoresist pattern is left behind on the substrate i.e., the exposed HMDS underlying is developed away, and that the patterned photoresist layer structure is subjected to etching followed by the stripping of the remaining patterned photoresist using a stripping agent i.e., the underlying patterned HMDS is also stripped to leave an etched substrate (etched structure of the substrate, see figure 1E) (claim 2). Allen, in [0220], discloses that the pattern developed has a line/space width that is less than 1 micron, and Allen, in [0116], discloses that the device formed (patterned device formed after etching processes) has the claimed linewidth (less than 1 micron) (claims 11-12). Allen, in [0003], [0174], discloses that the photoresist is a chemically amplified photoresist and can be subject to UV exposure at wavelengths of about 365nm, 436nm (claims 13-14).
The difference between the claims and Allen is that Allen does not disclose that the exposing of the photoresist includes a first and second exposures that overlap partially or that a horizontal movement between the substrate and mask occurs between the first and second exposures. Allen does not disclose that the temperature range of the first baking process (priming of the substrate with HMDS (promoter)), and the second baking process (post-application bake) does not overlap. Allen does not disclose the temperature range or the duration of the first baking process (performed after priming) as recited in claims 4-5.
Case, in the abstract, and [0061]-[0062], discloses that the exposure can be performed with a photomask such that a first illumination pattern (first exposure) and a subsequent second illumination pattern (second exposure) is performed by moving the substrate relative to the photomask (stationary photomask) such that an overlap region (partial overlap) is formed.
The difference between the claims and Allen in view of Case is that Allen in view of Case does not disclose that the temperature range of the first baking process and second baking process does not overlap. Allen in view of Case does not disclose the temperature range or duration of the first baking process recited in claims 4-5.
Sundararajan, in [0079], discloses that the wafer surface is vapor primed with HMDS (promoter) by a vapor prime and a dehydration bake at a temperature range of greater than 200 degrees for a period of about 30 seconds, and discloses in [0075], that the priming of the wafer occurs prior to coating the wafer with photoresist.
Therefore, it would be obvious to a skilled artisan to modify Allen by employing the method of using multiple exposures by stepping the substrate relative to the photomask as taught by Case because Case in [0065], discloses that moving the substrate between the exposures relative to the mask enables the complete exposure of a pattern, and Case, in [0059], and [0065], discloses that implementing multiple exposures by moving the substrate relative to the mask, that partially overlap enable the use of identical patterns or different patterns, and Case, in [0068], discloses that such repeat of illumination steps enables the exposure process in sub-threshold doses to be repeated as many times without catalyzing the photoresist in unwanted areas. It would be obvious to a skilled artisan to modify Allen in view of Case by employing the bake temperature and baking duration as taught by Sundararajan after priming the wafer with HMDS (promoter) because Allen teaches in [0168], and [0174], that the substrate is subjected to a vapor priming process using a priming agent, and Sundararajan, teaches in [0079] that the priming of the wafer surface that includes the subsequent dehydration bake at the claimed temperature enables vapor priming without contact of liquid HMDS and reduces particulate contamination, and vapor priming enables less consumption of HMDS (promoter).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over U. S. Patent Application Publication No. 2013/0260313 (hereinafter referred to as Allen) in view of U. S. Patent Application Publication No. 2003/0117598 (hereinafter referred to as Case) and U. S. Patent Application Publication No. 2010/0240555 (hereinafter referred to as Sundararajan) as applied to claims 1-2, 4-14, above, and further in view of U. S. Patent No. 5,512,328 (hereinafter referred to as Yoshimura).
Allen in view of Case and Sundararajan is discussed paragraph no. 3, above.
The difference between the claims and Allen in view of Case is that Allen in view of Case does not disclose the promoter layer thickness recited in claim 3.
Yoshimura, in col 8, lines 33-50, discloses that the HMDS is vapor primed to the substrate surface, and the thickness of the HMDS layer can be as low as 1nm.
Therefore, it would be obvious to a skilled artisan to modify Allen in view of Case and Sundararajan by employing the HMDS thickness taught by Yoshimura because Allen and Sundararajan teach vapor priming the substrate with HMDS prior to coating the photoresist, and Yoshimura teaches that using HMDS enables the formation of a monolayer thickness and at the same time provide a hydrophobic surface that maintains its etch resistance.
Claim(s) 15, is/are rejected under 35 U.S.C. 103 as being unpatentable over U. S. Patent Application Publication No. 2013/0260313 (hereinafter referred to as Allen) in view of U. S. Patent Application Publication No. 2003/0117598 (hereinafter referred to as Case) and U. S. Patent Application Publication No. 2010/0240555 (hereinafter referred to as Sundararajan) as applied to claims 1-2, and 4-14, above, and further in view of U. S. Patent Application Publication No. 2017/0315435 (hereinafter referred to as Mason).
Allen in view of Case and Sundararajan is discussed paragraph no. 3, above.
The difference between the claims and Allen in view of Case and Sundararajan is that Allen in view of Case and Sundararajan does not disclose the range of the path length of the relative movement between the mask and the substrate as recited in claim 15.
Mason, in [0037]-[0038], and [0062], discloses that the wafer is stepped relative to the mask wherein the path length during the relative displacement (in x -direction) between the substrate and mask can be at distances greater than 1nm (includes claimed 0.05 micron) and less than 200 micron (includes 5 micron).
Therefore, it would be obvious to a skilled artisan to modify Allen in view of Case and Sundararajan by employing the relative displacement lengths taught by Mason because Case teaches moving the substrate relative to the mask between exposures and Mason , in [0038], discloses that using the relative displacement of the photoresist-coated substrate with respect to the photomask enables nanopositioning of the stage (wafer holder) and enables the formation of many isolated structures that have customizable shape.
Response to Arguments
Applicant's arguments filed in the Amendment and Remarks on October 30, 2025, have been fully considered but they are not persuasive. With respect to applicant’s arguments that Allen or the cited references do not teach that the linewidth of the patterned device layer is equal to or less than a linewidth of the patterned photoresist layer, Allen, in [0220], discloses that the line/space pattern width of the developed pattern (includes the linewidth of the resist pattern developed) is about 22nm. Allen, in [0179], discloses that the patterned photoresist layer is used as an etch mask to transfer the pattern into the underlying substrate using an etch process, and Allen in [0116], discloses that the etch process used is for transferring the pattern with dimensions less than 50nm (sub 50 nm) and includes the dimension of the photoresist pattern i.e., 22nm and therefore the linewidth of the device pattern formed is at least equal to or less than the linewidth of the resist pattern and is less than 1 micron. Allen, as illustrated in figures 1D and 1E, discloses that the transfer of the pattern width from the resist pattern (44) to the underlying device (substrate, 66) is substantially the same dimension, and as cited in the preceding sentences above, the pattern width formed in the device (substrate) is less than 1 micron.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daborah Chacko-Davis whose telephone number is (571) 272-1380. The examiner can normally be reached on 9:30AM-6:00PM EST Mon-Fri. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark F. Huff can be reached on (571) 272-1385. The fax phone number for the organization where this application or proceeding is assigned is 571-272-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DABORAH CHACKO-DAVIS/Primary Examiner, Art Unit 1737 November 29, 2025.