Prosecution Insights
Last updated: April 19, 2026
Application No. 18/662,995

MEMORY DEVICE AND REFRESH METHOD THEREOF

Non-Final OA §102
Filed
May 13, 2024
Examiner
PHAM, LY D
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
To Grant
97%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
956 granted / 1018 resolved
+25.9% vs TC avg
Minimal +3% lift
Without
With
+3.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
17 currently pending
Career history
1035
Total Applications
across all art units

Statute-Specific Performance

§101
7.2%
-32.8% vs TC avg
§103
22.3%
-17.7% vs TC avg
§102
39.4%
-0.6% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1018 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 11 – 20 in the reply filed on 02 December 2025 is acknowledged. Claims 1 – 10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02 December 2025. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US Pat Pub 2023/0154522). The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Regarding claim 11, Kim et al. (US Pat Pub 2023/0154522) disclose a memory device (for example figs. 1 – 21 and all related texts), comprising: a memory cell array (MCA 110, fig. 1) including a plurality of memory cells (for example memory cell MC, fig. 2); and a refresh control circuit (refresh controller, para 0011) configured to: receive a first activation signal and a first activation row address corresponding to the first activation signal from an external device at a first time point (see abstract as well as “receive a first row address from an external device; select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values…”. See further para 0051, 0055 and 0127), and determine a victim row address to be refreshed on a victim row in the memory cell array based on an accumulation value (see abstract as well as “… select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values,”. See also para 0051), wherein the accumulation value is the number of activation signals received from a time point of receiving a refresh command from the external device to the first time point (referred to in para 0179 as “certain period of time”, the number of activations of the rows may be counted for a certain period of time. See also para 0007, 0010, etc…). Allowable Subject Matter Claims 20 is allowed. Claims 12 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior arts of record fail to teach or reasonably suggest the memory device as set forth above, further comprising, in combination, the features and limitations additionally claimed at least in claim 12. The prior arts of record also fail to teach or reasonably suggest a refresh method of a memory device, the method comprising, in combination: receiving a first activation signal and a first activation row address corresponding to the first activation signal at a first time point; generating a random number when the first activation signal is received; generating a reference value based on the number of activation signals received from an immediately previous first target row refresh (TRR) time point to the first time point; determining an attack row address based on a magnitude relationship between the random number and the reference value; determining a victim row address based on the attack row address; and performing a refresh operation on a victim row corresponding to the victim row address at a second TRR time point subsequent to the first time point. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See additional cited references for related disclosures to the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LY D. PHAM Examiner Art Unit 2827 /LY D PHAM/Primary Examiner, Art Unit 2827 December 17, 2025
Read full office action

Prosecution Timeline

May 13, 2024
Application Filed
Dec 17, 2025
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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MEMORY DEVICE, AND MEMORY SYSTEM AND OPERATION METHOD THEREOF
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Patent 12592294
APPARATUSES, SYSTEMS, AND METHODS FOR STORING ERROR INFORMATION AND PROVIDING RECOMMENDATIONS BASED ON SAME
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Patent 12586622
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2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
97%
With Interview (+3.4%)
1y 11m
Median Time to Grant
Low
PTA Risk
Based on 1018 resolved cases by this examiner. Grant probability derived from career allow rate.

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