Prosecution Insights
Last updated: April 19, 2026
Application No. 18/663,100

ELECTRONIC APPARATUS

Non-Final OA §102§103
Filed
May 14, 2024
Examiner
NICELY, JOSEPH C
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
97%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
603 granted / 781 resolved
+9.2% vs TC avg
Strong +20% interview lift
Without
With
+20.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
37 currently pending
Career history
818
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
49.4%
+9.4% vs TC avg
§102
21.3%
-18.7% vs TC avg
§112
19.8%
-20.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 781 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-12 are presented for examination. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 8, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hoegerl et al (US 2018/0211917 and Hoegerl hereinafter). As to claims 1-3, 8, and 12: Hoegerl discloses [claim 1] an electronic apparatus (Fig. 1; 10; [0021]), comprising: an insulator (11A; [0027]); a driving unit (12; [0021]), overlapped with the insulator (11A); an electronic unit (13; [0021]), overlapped with the insulator (11A); and a circuit unit (14; [0021]), electrically connected (through 17, 11C.3, 11C.4, 16.1, 16.2; [0021]-[0024]) to the driving unit (12), wherein the driving unit (12) receives a signal (driving signal) from the circuit unit (14) and drives the electronic unit (as the signal transfers from 14 to 12 and then to 13, the signal from 14 then drives the diode 13 through 12; [0021]); [claim 2] wherein the electronic unit (13) is an integrated circuit (the semiconductor chip 13 is interpreted to be an integrated circuit as it includes circuitry for semiconductor device(s); [0021]); [claim 3] wherein the electronic unit (13) is a diode (13 is a semiconductor diode chip; [0021]); [claim 8] wherein the driving unit (12) and the electronic unit (13) are disposed on a same surface (top surface) of the insulator (11A); [claim 12] wherein the circuit unit (14) is a chip (driver chip; [0021]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hoegerl in view of Hitora et al (US 2015/0325660 and Hitora hereinafter). Hoegerl discloses wherein the driving unit (12) comprises at least one transistor (IGBT; [0017]). Hoegerl fails to expressly disclose where the driving unit comprises a glass substrate, wherein the at least one transistor is disposed on the glass substrate. Hitora discloses a structure in Figs. 1 and 20 where an IGBT is formed on a glass substrate (5; [0072], [0091], and [0125]) with intervening layers. Given the teachings of Hitora, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Hoegerl by employing the well-known or conventional features of IGBT construction, such as displayed by Hitora, by employing a glass substrate under further substrate materials on which an IGBT can be formed in order to provide a substrate structure with good electrical properties ([0015]). Allowable Subject Matter Claims 4-6 and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JOSEPH C. NICELY Primary Examiner Art Unit 2813 /JOSEPH C. NICELY/Primary Examiner, Art Unit 2813 1/8/2026
Read full office action

Prosecution Timeline

May 14, 2024
Application Filed
Jan 08, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12588438
LAYER STRUCTURES INCLUDING DIELECTRIC LAYER, METHODS OF MANUFACTURING DIELECTRIC LAYER, ELECTRONIC DEVICE INCLUDING DIELECTRIC LAYER, AND ELECTRONIC APPARATUS INCLUDING ELECTRONIC DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12588255
SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12581961
SUBSTRATE HAVING A DIE POSITION MARK AND A SEMICONDUCTOR DIE STACK STRUCTURE INCLUDING SEMICONDUCTOR DIES STACKED ON THE SUBSTRATE
2y 5m to grant Granted Mar 17, 2026
Patent 12575341
METHOD FOR ANNEALING BONDING WAFERS
2y 5m to grant Granted Mar 10, 2026
Patent 12575160
BACKSIDE AND FRONTSIDE CONTACTS FOR SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
97%
With Interview (+20.1%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 781 resolved cases by this examiner. Grant probability derived from career allow rate.

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