CTNF 18/663,234 CTNF 101989 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 05/14/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1-2, 6-9, 11-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US Patent No 11,824,040) in view of Shih (US Patent No 12,354,965) . Regarding Claim 1, Wu (US Patent No 11,824,040) teaches a semiconductor package (electronic device 50, Figure 7, col 8, line 33), comprising a first redistribution structure (first redistribution structure 110, Figure 7, col 2, line 61); a first semiconductor die on the first redistribution structure (semiconductor die 530, Figure 7, col 18, lines 7-8); and a second semiconductor die on the first redistribution structure and side-by-side with the first semiconductor die (semiconductor die 530, Figure 1B, col 4, lines 56-59, teaches only one semiconductor die is shown as an example, but it is understood that more than one semiconductor dies or different types of semiconductor dies may be included within the electronic device) as claimed. Wu (US Patent No 11,824,040) teaches a second redistribution structure (second redistribution structure 350, Figure 7, col 13, lines 4-5) on the substrate; a third semiconductor die (device package 200A, Figure 7, col 13, line 56) on the second redistribution structure; and a fourth semiconductor die (device package 200B, Figure 7, col 13, lines 56-57) on the second redistribution structure. Wu (US Patent No 11,824,040) is silent to teach, a substrate on the first redistribution structure and surrounding each of the first semiconductor die and the second semiconductor die a bridge die on the substrate; a second redistribution structure on the substrate and around the bridge die; a third semiconductor die on the second redistribution structure and on the bridge die; and a fourth semiconductor die on the second redistribution structure and on the bridge die as claimed. In an analogous art, Shih (US Patent No 12,354,965) teaches, a substrate (first die 110, Figure 2, col 5 lines 12-15; teaches the first die may include a first substrate, a first dielectric layer, a plurality of first device elements, a plurality of first conductive layers, and a plurality of first conductive pads; here the entire structure of the first die is considered analogous to the claimed substrate) on the first redistribution structure and surrounding each of the first semiconductor die and the second semiconductor die; a bridge die (bridge layer 215, Figure 11, col 5, line 10, teaches a plurality of bridge layers) on the substrate (Col 5 lines 12-15; teaches the first die may include a first substrate, a first dielectric layer, a plurality of first device elements, a plurality of first conductive layers, and a plurality of first conductive pads; here the entire structure of the first die is considered analogous to a substrate); a second redistribution structure (first redistribution structure 210, Figure 11, col 5, line 7-10, teaches a first redistribution structure may be formed on the first die, wherein the first redistribution structure may include a plurality of conductive layers and a plurality of bridge layers) on the substrate and around the bridge die; a third semiconductor die (third die 130, Figure 11, col 10, line 40-42, teaches the first redistribution structure may be bonded onto the second die and the third die) on the second redistribution structure and on the bridge die; and a fourth semiconductor die (second die 120, Figure 11, col 10, line 40-42, teaches the first redistribution structure may be bonded onto the second die and the third die) on the second redistribution structure and on the bridge die. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Wu (US Patent No 11,824,040) to incorporate the teachings of Shih (US Patent No 12,354,965) by substituting the first insulating layer of Wu (US Patent No 11,824,040) with the substrate of Shih (US Patent No 12,354,965). Doing so allows the integration of embedded traces which removes the need to manufacture conductive posts thereby decreasing turnaround times and improving yield. Further, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the second redistribution structure of Wu (US Patent No 11,824,040) with the first redistribution structure of Shih (US Patent No 12,354,965) thereby incorporating a bridge die into the second redistribution structure. Doing so offers a shorter electrical path length between the third and fourth semiconductor dies. Regarding claim 2, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 1, and Wu (US Patent No 11,824,040) further teaches wherein each of the first semiconductor die and the second semiconductor die comprises a plurality of through-silicon vias (through semiconductor vias (TSVs) 534, Figure 7, col 17, line 57); and the plurality of through-silicon vias electrically connects the first redistribution structure to the second redistribution structure (col 16, lines 14-17, teaches the second redistribution structure may be electrically coupled to the first redistribution structure through…the TSVs). Regarding claim 3, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 1, and Wu (US Patent No 11,824,040) further teaches wherein the substrate comprises a first through opening and a second through opening (Figure 1A, col 2 line 60 – col 4 line 33, teaches an opening on a first redistribution layer but is not limited to a single opening); the first semiconductor die is disposed within the first through opening; and the second semiconductor die is disposed within the second through opening (Figure 1B, col 4, lines 34-35, teaches a semiconductor die may be provided and disposed over the first redistribution structure). PNG media_image1.png 411 708 media_image1.png Greyscale Regarding claim 6, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 1, and Shih (US Patent No 12,354,965) further teaches wherein the bridge die comprises a plurality of second wire lines that electrically connect the third semiconductor die to the fourth semiconductor die (col 1, lines 48-50, teaches a bridge layer…electrically connected the second die and the third die). Regarding claim 7, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 1, and Shih (US Patent No 12,354,965) further teaches wherein the third semiconductor die comprises plurality of connection members (first connecting layer 513, Figure 11, col 11, lines 45-46); and at least one of the plurality of connection members is connected to the second redistribution structure, and the remaining connection members of the plurality of connection members are connected to the bridge die. PNG media_image2.png 376 799 media_image2.png Greyscale Regarding claim 8, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 1, and Shih (US Patent No 12,354,965) further teaches wherein the fourth semiconductor die comprises plurality of connection members (first connecting layer 513, Figure 11, col 11, lines 45-46); and at least one of the plurality of connection members is connected to the second redistribution structure, and the remaining connection members of the plurality of connection members are connected to the bridge die. PNG media_image3.png 376 799 media_image3.png Greyscale Regarding Claim 9, Wu (US Patent No 11,824,040) teaches a semiconductor package (electronic device 50, Figure 7, col 8, line 33), comprising a first redistribution structure (first redistribution structure 110, Figure 7, col 2, line 61); a first semiconductor die on the first redistribution structure (semiconductor die 530, Figure 7, col 18, lines 7-8); a second semiconductor die on the first redistribution structure and side-by-side with the first semiconductor die (semiconductor die 530, Figure 1B, col 4, lines 56-59, teaches only one semiconductor die is shown as an example, but it is understood that more than one semiconductor dies or different types of semiconductor dies may be included within the electronic device; and a surface-mount device (SMD) disposed on the third semiconductor die (col 8, lines 27-30, teaches the device packages include…a surface mount device (SMD)) as claimed. Wu (US Patent No 11,824,040) teaches a second redistribution structure (second redistribution structure 350, Figure 7, col 13, lines 4-5) on the substrate; a third semiconductor die (device package 200A, Figure 7, col 13, line 56) on the second redistribution structure; and a fourth semiconductor die (device package 200B, Figure 7, col 13, lines 56-57) on the second redistribution structure. Wu (US Patent No 11,824,040) is silent to teach, a first molding material surrounding the first semiconductor die and the second semiconductor die, on the first redistribution structure; a substrate on the first redistribution structure and surrounding each of the first semiconductor die and the second semiconductor die; a bridge die on the substrate; a second redistribution structure on the substrate and around the bridge die; a third semiconductor die on the second redistribution structure and on the bridge die; a fourth semiconductor die on the second redistribution structure and on the bridge die; and a second molding material surrounding the third semiconductor die and the fourth semiconductor die, on the second redistribution structure. In an analogous art, Shih (US Patent No 12,354,965) teaches, a first molding material (second molding layer 413, Figure 11, col 13, line 38) surrounding the first semiconductor die and the second semiconductor die, on the first redistribution structure (Col 13, lines 38-40, teaches a second molding layer may be formed…to cover the first die); a substrate (Col 5 lines 12-15; teaches the first die may include a first substrate, a first dielectric layer, a plurality of first device elements, a plurality of first conductive layers, and a plurality of first conductive pads; here the substrate of the first die is considered analogous to the claimed substrate) on the first redistribution structure and surrounding each of the first semiconductor die and the second semiconductor die a bridge die (bridge layer 215, Figure 11, col 5, line 10, teaches a plurality of bridge layers) on the substrate; a second redistribution structure (first redistribution structure 210, Figure 11, col 5, line 7-10, teaches a first redistribution structure may be formed on the first die, wherein the first redistribution structure may include a plurality of conductive layers and a plurality of bridge layers) on the substrate and around the bridge die; a third semiconductor die (third die 130, Figure 11, col 10, line 40-42, teaches the first redistribution structure may be bonded onto the second die and the third die) on the second redistribution structure and on the bridge die; a fourth semiconductor die (second die 120, Figure 11, col 10, line 40-42, teaches the first redistribution structure may be bonded onto the second die and the third die) on the second redistribution structure and on the bridge die; and a second molding material (first molding layer 411, Figure 11, col 10, line 60) surrounding the third semiconductor die and the fourth semiconductor die, on the second redistribution structure (claim 11, col 21, lines 57-59, teaches a first molding layer positioned on the second redistribution structure and surrounding the second die and the third die). Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Wu (US Patent No 11,824,040) to incorporate the teachings of Shih (US Patent No 12,354,965) by substituting the first insulating layer of Wu (US Patent No 11,824,040) with the first molding layer and substrate of Shih (US Patent No 12,354,965). Doing so allows the encapsulation of the first and second semiconductor dies and integration of embedded traces which removes the need to manufacture conductive posts thereby decreasing turnaround times and improving yield. Further, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the second redistribution structure of Wu (US Patent No 11,824,040) with the first redistribution structure of Shih (US Patent No 12,354,965) thereby incorporating a bridge die into the second redistribution structure. Doing so offers a shorter electrical path length between the third and fourth semiconductor dies. Regarding claim 11, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 9, and Wu (US Patent No 11,824,040) further teaches wherein the first semiconductor die comprises an application processor (AP) (Col 5, lines 43-47, teaches the semiconductor die includes one or more types of dies selected from application-specific integrated circuit (ASIC) dies, analog dies, sensor dies, wireless and radio frequency dies, voltage regulator dies or memory dies). Regarding claim 12, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 9, and Wu (US Patent No 11,824,040) further teaches wherein the second semiconductor die comprises a communication processor (CP) (Col 5, lines 43-47, teaches the semiconductor die includes one or more types of dies selected from application-specific integrated circuit (ASIC) dies, analog dies, sensor dies, wireless and radio frequency dies, voltage regulator dies or memory dies). Regarding claim 13, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 9, and Shih (US Patent No 12,354,965) further teaches wherein the substrate comprises an embedded trace substrate (ETS). PNG media_image4.png 352 790 media_image4.png Greyscale Regarding claim 14, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 9. Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) are silent to teach wherein the bridge die comprises a silicon bridge die. Wu (US Patent No 11,824,040) teaches a semiconductor die may be used as a bridge die (Col 5, line 48, teaches the semiconductor die is a bridge die) which may be a silicon bridge (col 5, lines 48-49 teaches the semiconductor die is a bridge die (e.g., a silicon bridge)). Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filling date of the claimed invention to have modified the teachings of Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) by substituting the bridge die of Shih (US Patent No 12,354,965) with the bridge die of Wu (US Patent No 11,824,040) to incorporate a silicon bridge die. Regarding claim 15, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 9. Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) are silent to teach, wherein the third semiconductor die comprises a high bandwidth memory (HBM). Wu (US Patent No 11,824,040) teaches a semiconductor die that may be a memory die which can include high bandwidth memory (Col 7, lines 50-54, teaches the device package includes an integrated circuit (IC) die packaged in an encapsulating layer. The IC die may be or may include a memory die, a processor die, a logic die, and/or a combination thereof, etc.). Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filling date of the claimed invention to have modified the teachings of Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) by substituting the device package of Wu (US Patent No 11,824,040) with the semiconductor die of Wu (US Patent No 11,824,040) to incorporate a high bandwidth memory. Regarding claim 16, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 9. Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) are silent to teach, wherein the fourth semiconductor die comprises a radio frequency IC (RFIC) chip, a display driver IC (DDI) chip, a sensor chip, or a power management IC (PMIC) chip. Wu (US Patent No 11,824,040) further teaches a semiconductor die (Col 5, lines 43-47, teaches the semiconductor die includes one or more types of dies selected from application-specific integrated circuit (ASIC) dies, analog dies, sensor dies, wireless and radio frequency dies, voltage regulator dies or memory dies.). Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filling date of the claimed invention to have modified the teachings of Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) to substitute the device package of Wu (US Patent No 11,824,040) with the semiconductor die of Wu (US Patent No 11,824,040) to incorporate a sensor die. The combination of one known element with another is likely to be obvious when predictable results are achieved. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 415-421, USPQ2d 1385, 1395 – 97 (2007). Regarding Claim 17, Wu (US Patent No 11,824,040) teaches a manufacturing method of a semiconductor package (electronic device 50, Figure 7, col 8, line 33), the manufacturing method comprising forming a first redistribution structure (Claim 17, col 30, line 11, teaches forming the first redistribution structure); mounting a first semiconductor die on the first redistribution structure (Claim 18, col 30, lines 20-21, teaches attaching a backside of the semiconductor die to the first redistribution structure) and within the first through opening, and mounting a second semiconductor die on the first redistribution structure (Claim 18, col 30, lines 20-21, teaches attaching a backside of the semiconductor die to the first redistribution structure) and within the second through opening; forming a second redistribution structure on the first semiconductor die, the second semiconductor die, and the substrate (Claim 16, col 29, lines 27-28, teaches forming a second redistribution structure on the molding layer, the semiconductor die); and mounting a third semiconductor die and a fourth semiconductor die on the second redistribution structure (Claim 16, col 29, lines 36-38, teaches mounting a device package on the second side of the second redistribution structure, wherein the device package comprises a packaged integrated circuit die) and on the bridge die as claimed. Wu (US Patent No 11,824,040) is silent to teach, bonding a substrate comprising a first through opening and a second through opening on the first redistribution structure; and mounting a bridge die within the second redistribution structure. In an analogous art, Shih (US Patent No 12,354,965) teaches bonding a substrate comprising a first through opening and a second through opening on the first redistribution structure (Col 7, lines1-3, teaches the first redistribution structure may be formed on the front surface of the first die); and mounting a bridge die within the second redistribution structure (Col 7, lines 58-59, teaches the plurality of bridge layers may be formed in the first redistribution dielectric layer). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filling date of the claimed invention to have modified the teachings of Wu (US Patent No 11,824,040) by substituting the second redistribution layer structure with the first redistribution layer of Shih (US Patent No 12,354,965) thereby incorporating a bridge die structure within the second redistribution layer structure. Doing so offers a shorter electrical path length between the third and fourth semiconductor dies. Regarding claim 20, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 17, and Wu (US Patent No 11,824,040) further teaches further comprising mounting a surface-mount device on the third semiconductor die (Col 8, lines 27-30, teaches the device packages include…a surface mount device (SMD)). Claim 4 and 19 are rejected under 35 U.S.C. 103 as unpatentable over Wu (US Patent No 11,824,040) in view of Shih (US Patent No 12,354,965) and Xie (US Patent Application Publication 20,250,218,953). Regarding claim 4, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 1. Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) are silent to teach wherein the second redistribution structure comprises a third through opening; and the bridge die is disposed within the third through opening. In an analogous art, Xie (US Patent Application Publication 20,250,218,953) teaches wherein the second redistribution structure (build-up region 208, Figure 3C, paragraph 0027, lines 5-6, teaches the build-up regions can include redistribution layers (RDLs)) comprises a third through opening (cavity 222, Figure 3C, paragraph 0030, line 4); and the bridge die is disposed within the third through opening (Claim 18, Figure 3D, teaches a method comprising: providing build-up layers on a core of a package substrate; providing a cavity in the build-up layers, a first surface of the cavity to include a conductive pad; positioning a bridge die in the cavity on the first surface,). Therefore, it would have been obvious for someone of ordinary sill in the art before the effective filling date of the claimed invention to have modified the teachings of Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) with Xie (US Patent Application Publication 20,250,218,953) by creating a cavity in the second redistribution layer to incorporate a bridge die structure to provide a shorter electrical path between semiconductor dies. Regarding claim 19, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 17, and Xie (US Patent Application Publication 20,250,218,953) further teaches wherein the forming the second redistribution structure comprises forming a third through opening in the second redistribution structure (Claim 18, Figure 3C, teaches providing a cavity in the build-up layers) . 07-21-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US Patent No 11,824,040) in view of Shih (US Patent No 12,354,965) and Kim (US Patent Application Publication No 20,200,243,422) . Regarding claim 5, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 1. Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) are silent to teach wherein the bridge die comprises a plurality of first wire lines that electrically connect the third semiconductor die to the substrate and the fourth semiconductor die to the substrate. In an analogous art, Kim (US Patent Application Publication No 20,200,243,422) teaches wherein the bridge die comprises a plurality of first wire lines that electrically connect the third semiconductor die to the substrate (Paragraph 0029, lines 5-7, teaches the first bridge die may function as an interconnection member for electrically connecting the first semiconductor die to the package substrate) and the fourth semiconductor die to the substrate. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filling date of the claimed invention to have modified the teachings of Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) to include in the internal wiring structure of the bridge die to connect the semiconductor dies to the substrate thereby electrically connecting the semiconductor dies to the redistribution structure . 07-21-aia AIA Claim 10 is rejected under 35 U.S.C 103 as being unpatentable over Wu (US Patent No 11,824,040) in view of Shih (US Patent No 12,354,965) and Yu (US Patent Application Publication 20,220,359,327) . Regarding claim 10, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 9. Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) are silent to teach wherein the surface-mount device comprises an integrated stack capacitor (ISC). In an analogous art Yu (US Patent Application Publication 20,220,359,327) teaches wherein the surface-mount device (first surface device 207, col 0075, lines 5-8, teaches the first surface device may be a surface mount device (SMD)…that comprise passive devices such as resistors, inductors, capacitors, jumpers, combinations of these, or the like) comprises an integrated stack capacitor (ISC). Therefore, it would have been obvious for someone of ordinary sill in the art before the effective filling date of the claimed invention to have modified the teachings of Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) by substituting the SMDs of Wu (US Patent No 11,824,040) with the SMDs of Yu (US Patent Application Publication 20,220,359,327) to incorporate an integrated stack capacitor thereby maximizing the electrical characteristics of the semiconductor package . 07-21-aia AIA Claim 18 is rejected under 35 U.S.C 103 as being unpatentable over Wu (US Patent No 11,824,040) in view of Shih (US Patent No 12,354,965) and Wu (US Patent Application Publication 20,230,009,506) . Regarding claim 18, Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) teach the device as claimed in claim 17. Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) are silent to teach, wherein the substrate is bonded to the first redistribution structure by a thermal compression. In an analogous art, Wu (US Patent Application Publication 20,230,009,506) teaches wherein the substrate is bonded to the first redistribution structure by a thermal compression (Paragraph 0028, lines 3-9, teaches the wiring substrates are coupled with the redistribution structure by the conductive joints, such as solder, between the topmost conductive pattern of the redistribution structure and the wiring substrate, and then a high temperature process, such as reflow or thermal compression bonding, may be performed to melt the conductive joints). Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filling date of the claimed invention to have modified the teachings of Wu (US Patent No 11,824,040) and Shih (US Patent No 12,354,965) by bonding a redistribution layer to a substrate using the thermal compression process taught by Wu (US Patent Application Publication 20,230,009,506). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached Monday – Friday 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.M.A./ Examiner, Art Unit 2898 /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 18/663,234 Page 2 Art Unit: 2898 Application/Control Number: 18/663,234 Page 3 Art Unit: 2898 Application/Control Number: 18/663,234 Page 4 Art Unit: 2898 Application/Control Number: 18/663,234 Page 5 Art Unit: 2898 Application/Control Number: 18/663,234 Page 6 Art Unit: 2898 Application/Control Number: 18/663,234 Page 7 Art Unit: 2898 Application/Control Number: 18/663,234 Page 8 Art Unit: 2898 Application/Control Number: 18/663,234 Page 9 Art Unit: 2898 Application/Control Number: 18/663,234 Page 10 Art Unit: 2898 Application/Control Number: 18/663,234 Page 11 Art Unit: 2898 Application/Control Number: 18/663,234 Page 12 Art Unit: 2898 Application/Control Number: 18/663,234 Page 13 Art Unit: 2898 Application/Control Number: 18/663,234 Page 14 Art Unit: 2898 Application/Control Number: 18/663,234 Page 15 Art Unit: 2898
Prosecution Insights