Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Species I (claims 1-14) in the reply filed on 08/03/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 14, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jun et al. (Pub. No.: US 2022/0102491 A1).
Regarding Claim 1, Jun et al. discloses an integrated circuit semiconductor device, comprising: a substrate (Par. 0024; Figs. 1-2C – substrate 110); an active fin on the substrate (Par. 0024-0025; Figs. 1-2C – active fin FA);
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a plurality of gate structures spaced apart from one another on the active fin in a first direction parallel to an upper surface of the substrate, each of the plurality of gate structures extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction (Par. 0026-0029; Figs. 1-2C – gate structures GL); an interlayer insulation layer configured to electrically insulate the plurality of gate structures on the active fin (Par. 0029-0032; Figs. 1-2C – interlayer insulation layer 162); a plurality of gate contacts spaced apart from one another on the plurality of gate structures (Par. 0033-0036; Figs. 1-2C – gate contacts CB); a plurality of active contacts spaced apart from one another at opposite sides of the plurality of gate structures in the first direction, each of the plurality of active contacts passing through the interlayer insulation layer in a third direction perpendicular to the upper surface of the substrate and contacting the active fin (Par. 0033-0036; Figs. 1-2C – active contacts CA1); an etch stopping layer on the plurality of gate structures, the interlayer insulation layer, the plurality of gate contacts, and the plurality of active contacts (Par. 0032; Figs. 1-2C – etch stopping layer 182A); and a plurality of diffusion break regions between the plurality of active contacts in the first direction, the plurality of diffusion break regions at least partially filling gate trenches passing through the etch stopping layer and the interlayer insulation layer in the third direction and at least partially filling fin recesses cutting the active fin under the gate trenches (Par. 0036-0040; Figs. 1-2C – diffusion break region 120A).
Regarding Claim 2, Jun et al. , as applied to claim 1, discloses
the integrated circuit semiconductor device, wherein the active fin further comprises a plurality of source and drain regions spaced apart from each other at opposite sides of the plurality of gate structures in the first direction, and the plurality of active contacts electrically contact the plurality of source and drain regions (Par. 0030-0036; Figs. 1-2C – source/drain regions 172).
Regarding Claim 3, Jun et al. , as applied to claim 1, discloses
the integrated circuit semiconductor device, wherein each of the plurality of gate structures comprises gate electrodes and gate spacers formed on opposite sidewalls of the gate electrodes (Par. 0026-0030; Figs. 1-2C – part of gate insulating film 118 which is formed on opposite sidewalls of gate electrode GL is considered as the gate spacer).
Regarding Claim 4, Jun et al. , as applied to claim 3, discloses
the integrated circuit semiconductor device, wherein the plurality of active contacts pass through the interlayer insulation layer and the gate spacers and electrically contact the active fin (Par. 0033-0036; Figs. 1-2C – active contacts CA1).
Regarding Claim 5, Jun et al. , as applied to claim 3, discloses
the integrated circuit semiconductor device, wherein the plurality of diffusion break regions are buried in the gate trenches passing through the etch stopping layer, the interlayer insulation layer, and the gate spacers and in the fin recesses connecting with the gate trenches under the gate trenches (Par. 0036-0040; Figs. 1-2C – diffusion break region 120A).
Regarding Claim 6, Jun et al. , as applied to claim 1, discloses
the integrated circuit semiconductor device, wherein the plurality of diffusion break regions and the etch stopping layer comprise a same material (Par. 0032-0040; Figs. 1-2C – the central portion 128 of diffusion break region 120A is potentially formed of silicon nitride (Par. 0038); the etch stopping layer 182A is also potentially formed of silicon nitride (Par. 0032)).
Regarding Claim 7, Jun et al. , as applied to claim 1, discloses
the integrated circuit semiconductor device, wherein lower ends of the plurality of diffusion break regions are at a level which is lower than lower ends of the plurality of active contacts relative to the upper surface of the substrate (Par. 0036-0040; Figs. 2A-2C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 102(a)(1) as anticipated by Jun et al. (Pub. No.: US 2022/0102491 A1), as applied to claim 1, or, in the alternative, under 35 U.S.C. 103 as obvious over Jun et al. (Pub. No.: US 2022/0102491 A1), as applied to claim 1, in view of Yu et al. (Pub. No. : US 2016/0190130 A1).
Regarding Claim 8, Jun et al. , as applied to claim 1, discloses the integrated circuit semiconductor device, wherein the plurality of diffusion break regions comprise single diffusion break regions configured as one insulation layer (Par. 0036-0040; Figs. 1-2C – this prior art teaches diffusion break region 120A although comprises of spacers 122, 124, 126 and isolation insulating film 128 may be all formed of the same material, such as silicon nitride (SiN)). In the alternative, assuming arguendo that Jun et al. is not emphatic enough regarding the integrated circuit semiconductor device, wherein the plurality of diffusion break regions comprise single diffusion break regions configured as one insulation layer, Yu et al., at least implicitly teaches the integrated circuit semiconductor device, wherein the plurality of diffusion break regions comprise single diffusion break regions configured as one insulation layer (Par. 0032-0035; Fig. 2L – this prior art teaches diffusion break region 270 is formed of a single insulation layer such as silicon oxide). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Yu et al. to adapt the integrated circuit semiconductor device, wherein the plurality of diffusion break regions of comprise single diffusion break regions Jun et al. configured as one insulation layer in order to simplify the fabrication process.
Claims 9-12 and 14 are rejected under 35 U.S.C. 103 as obvious over Jun et al. (Pub. No.: US 2022/0102491 A1) in view of Bouche et al. (Pub. No. : US 2015/0311199 A1).
Regarding Claim 9, Jun et al. discloses an integrated circuit semiconductor device, comprising: a substrate (Par. 0024; Figs. 1-2C – substrate 110);
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a plurality of active fins extending in a first direction on the substrate and arranged apart from one another in a second direction intersecting the first direction, the first and second directions being parallel to an upper surface of the substrate (Par. 0024-0025; Figs. 1-2C – active fins FA); a plurality of gate structures extending in the second direction on the plurality of active fins and arranged apart from one another in the first direction (Par. 0026-0029; Figs. 1-2C – gate structures GL); an interlayer insulation layer configured to insulate the plurality of gate structures on the plurality of active fins (Par. 0029-0032; Figs. 1-2C – interlayer insulation layer 162); a plurality of gate contacts on the plurality of gate structures and arranged apart from one another in the first direction Par. 0033-0036; Figs. 1-2C – gate contacts CB); a plurality of active contacts extending in the second direction at both sides of the plurality of gate structures arranged apart from one another in the first direction, the plurality of active contacts passing through the interlayer insulation layer and contacting the plurality of active fins (Par. 0033-0036; Figs. 1-2C – active contacts CA1); an etch stopping layer on the plurality of gate structures, the interlayer insulation layer, the plurality of gate contacts, and the plurality of active contacts (Par. 0032; Figs. 1-2C – etch stopping layer 182A); and a plurality of diffusion break regions between the plurality of active contacts, the plurality of diffusion break regions being buried in gate trenches passing through the etch stopping layer and the interlayer insulation layer and in fin recesses cutting the plurality of active fins under the gate trenches (Par. 0036-0040; Figs. 1-2C – diffusion break region 120A). Jun et al. does not explicitly disclose a plurality of gate contacts on the plurality of gate structures and arranged apart from one another in the second direction. However, Bouche et al. teaches a plurality of gate contacts on the plurality of gate structures and arranged apart from one another in the second direction (Par. 0017-0020; Fig. 1 – active fins 115; gate structure 120; gate
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contacts 125; each gate structure has plurality of contacts arranged apart from one another in the second direction; this helps reduce gate contact resistance). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Bouche et al. to adapt the integrated circuit semiconductor device, wherein a plurality of gate contacts are on the plurality of gate structures of Jun et al. and arranged apart from one another in the second direction in order to achieve reduced gate resistance.
Regarding Claim 10, modified Jun et al., as applied to claim 9, discloses
the integrated circuit semiconductor device, wherein the plurality of active fins further comprise a plurality of source and drain regions arranged apart from each other at opposite sides of the plurality of gate structures, and the plurality of active contacts electrically contact the plurality of source and drain regions (Jun et al. - Par. 0030-0036; Figs. 1-2C – source/drain regions 172).
Regarding Claim 11, modified Jun et al. , as applied to claim 9, discloses
the integrated circuit semiconductor device, wherein the plurality of gate structures comprise gate electrodes and gate spacers on opposite sidewalls of the gate electrodes (Par. 0026-0030; Figs. 1-2C – part of gate insulating film 118 which is formed on opposite sidewalls of gate electrode GL is considered as the gate spacer), and the plurality of active contacts pass through the interlayer insulation layer and the gate spacers in a third direction perpendicular to the upper surface of the substrate and electrically contact the plurality of active fins (Jun et al. - Par. 0033-0036; Figs. 1-2C – active contacts CA1).
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Regarding Claim 12, modified Jun et al. , as applied to claim 9, discloses
the integrated circuit semiconductor device, wherein the plurality of gate structures comprise gate electrodes and gate spacers on opposite sidewalls of the gate electrodes (Par. 0026-0030; Figs. 1-2C – part of gate insulating film 118 which is formed on opposite sidewalls of gate electrode GL is considered as the gate spacer), and the plurality of diffusion break regions are buried in the gate trenches passing through the etch stopping layer, the interlayer insulation layer, and the gate spacers and in the fin recesses connecting with the gate trenches under the gate trenches (Jun et al. - Par. 0036-0040; Figs. 1-2C – diffusion break region 120A).
Regarding Claim 14, modified Jun et al. , as applied to claim 9, discloses
the integrated circuit semiconductor device, wherein lower ends of the plurality of diffusion break regions are at a level which is lower than lower ends of the plurality of active contacts relative to the upper surface of the substrate (Jun et al. - Par. 0036-0040; Figs. 2A-2C).
Claim 13 is rejected under 35 U.S.C. 103 as obvious over Jun et al. (Pub. No.: US 2022/0102491 A1) and Bouche et al. (Pub. No. : US 2015/0311199 A1), as applied to claim 9, or, in the alternative, under 35 U.S.C. 103 as obvious over Jun et al. (Pub. No.: US 2022/0102491 A1) and Bouche et al. (Pub. No. : US 2015/0311199 A1), as applied to claim 9, further in view of Yu et al. (Pub. No. : US 2016/0190130 A1).
Regarding Claim 13, Jun et al. , as applied to claim 9, discloses
the integrated circuit semiconductor device, wherein the plurality of diffusion break regions comprise void-free diffusion break regions where a void is not formed, and the plurality of diffusion break regions comprise single diffusion break regions configured as one insulation layer (Jun et al. - Par. 0036-0040; Figs. 1-2C – this prior art teaches diffusion break region 120A although comprises of spacers 122, 124, 126 and isolation insulating film 128 may be all formed of the same material, such as silicon nitride (SiN)). In the alternative, assuming arguendo that Jun et al. is not emphatic enough regarding the integrated circuit semiconductor device, wherein the plurality of diffusion break regions comprise single diffusion break regions configured as one insulation layer, Yu et al., at least implicitly teaches the integrated circuit semiconductor device, wherein the plurality of diffusion break regions comprise single diffusion break regions configured as one insulation layer (Par. 0032-0035; Fig. 2L – this prior art teaches diffusion break region 270 is formed of a single insulation layer such as silicon oxide). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Yu et al. to adapt the integrated circuit semiconductor device, wherein the plurality of diffusion break regions of comprise single diffusion break regions Jun et al. configured as one insulation layer in order to simplify the fabrication process.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Banna et al. (Patent No.: US 8609510 B1) – This prior art teaches an integrated circuit semiconductor device, comprising: a substrate (109); an active fin on the substrate (108); a plurality of gate structures (102) spaced apart from one another on the active fin in a first direction parallel to an upper surface of the substrate, each of the plurality of gate structures extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; an interlayer insulation layer (118) configured to electrically insulate the plurality of gate structures on the active fin; 136) between the plurality of active contacts in the first direction, the plurality of diffusion break regions at least partially filling gate trenches passing through Fig. 10).
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08/20/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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