DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed May 14, 2024.
Claims 1-20 are pending. Claims 1, 14 and 18 are independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on May 14, 2024. This IDS has been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Mokhlesi (U.S. 2008/0304316) in view of Kobayashi et al. (U.S. 2002/0057595; hereinafter “Kobayashi”).
Regarding independent claim 1, Mokhlesi teaches a non-volatile storage apparatus (Fig. 1), comprising:
non-volatile memory cells (Fig. 4: 10, see also Abstract);
a plurality of bit lines connected to the non-volatile memory cells (Fig. 4: Bit lines); and
a control circuit (Fig. 1: 110) connected to the non-volatile memory cells (Fig. 4: 10) and the bit lines (Fig. 4: Bit lines), memory cells connected to a first bit line of the plurality of bit lines (Fig. 19: cell connected to 36) and memory cells connected to one or more other bit lines of the plurality of bit lines (Fig. 19: cell connected to other 36), and the control circuit is configured to perform a sensing process by determining an average of an output from the first bit line and one or more outputs from the one or more other bit lines (see page 13, par. 0158).
However, Mokhlesi is silent with respect to memory cells connected to a first bit line of the plurality of bit lines are configured to store information that is redundant of information stored in memory cells connected to one or more other bit lines of the plurality of bit lines.
Similar to Mokhlesi, Kobayashi teaches a non-volatile storage apparatus (Fig. 1) comprising non-volatile memory cells (see Abstract) and a plurality of bit lines connected to the non-volatile memory cells (Fig. 3: BLs).
Furthermore, Kobayashi teaches memory cells connected to a first bit line of the plurality of bit lines are configured to store information that is redundant of information stored in memory cells connected to one or more other bit lines of the plurality of bit lines (“one bit fata is stored in the pair of cells,” see page 4, par. 0063).
Since Kobayashi and Mokhlesi are from the same field of endeavor, the teachings described by Kobayashi would have been recognized in the pertinent art of Mokhlesi.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kobayashi with the teachings of Mokhlesi for the purpose of high speed reading operation, see Kobayashi’s page 4, par. 0063.
Regarding claim 2, Mokhlesi in combination with Kobayashi teaches the limitations with respect to claim 1.
Furthermore, Mokhlesi teaches wherein the control circuit is configured to perform the sensing process by determining an average of current in the first bit line and current in the one or more other bit lines (see page 13, par. 0158).
Regarding claim 4, Mokhlesi in combination with Kobayashi teaches the limitations with respect to claim 2.
Furthermore, Kobayashi teaches wherein the first bit line and the one or more other bit lines are physically shorted together (Fig. 3: short circuit).
Regarding claim 5, Mokhlesi in combination with Kobayashi teaches the limitations with respect to claim 2.
Furthermore, Kobayashi teaches one or more switches (Fig. 3: 57a-57d) connected to the first bit line (Fig. 3: BL1), the one or more other bit lines (Fig. 3: BL2) and the control circuit (Fig. 3: 17-18) to selectively short the first bit line to the one or more other bit lines (see page 4, par. 0063-0064).
Claims 3 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Mokhlesi and Kobayashi as applied to claim 2 above, and further in view of Lue et al. (U.S. 2020/0192971; hereinafter “Lue”).
Regarding claim 3, Mokhlesi and Kobayashi teaches the limitations with respect to claim 2.
However, the combination is silent with respect to the control circuit is configured to determine the average by: sensing a total current flowing in the first bit line while first bit line is connected to and receiving current from multiple non-volatile memory cells in different blocks; sensing a total current flowing in the one or more other bit lines while the one or more other bit lines are connected to and receiving current from multiple non-volatile memory cells in the different blocks; and calculating an average of the sensed total current flowing in the first bit line and the sensed total current flowing in the one or more other bit lines.
Lue teaches a control circuit configured to determine the average by:
sensing a total current flowing in the first bit line while first bit line is connected to and receiving current from multiple non-volatile memory cells in different blocks (Fig. 3: current flowing through BL(1) connected to a plurality of memory cells in blocks 1 and 2);
sensing a total current flowing in the one or more other bit lines while the one or more other bit lines are connected to and receiving current from multiple non-volatile memory cells in the different blocks (Fig. 3: current flowing through BL(2) connected to a plurality of memory cells in blocks 1 and 2); and
calculating an average of the sensed total current flowing in the first bit line and the sensed total current flowing in the one or more other bit lines (see page 7, par. 0094).
Since Lue, Kobayashi and Mokhlesi are from the same field of endeavor, the teachings described by Lue would have been recognized in the pertinent art of Mokhlesi in combination with Kobayashi.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lue with the teachings of Mokhlesi in combination with Kobayashi for the purpose of large-scale computation, see Lue’s page 4, par. 0056.
Regarding claim 8, Mokhlesi in combination with Kobayashi teaches the limitations with respect to claim 1.
Furthermore, Mokhlesi teaches the non-volatile memory cells are grouped into a plurality of blocks (see pages 5-6, par. 0082-0083).
However, the combination is silent with respect to each of the bit lines of the plurality of bit lines are connected to non-volatile memory cells in every block of the plurality of blocks; and the control circuit is configured to perform the sensing process by determining an average of current in the first bit line and current in the one or more other bit lines while the first bit line and the one or more other bit lines are concurrently receiving current from non-volatile memory cells in multiple blocks.
Lue teaches each of the bit lines of the plurality of bit lines are connected to non-volatile memory cells in every block of the plurality of blocks (Fig. 3: BL(1) and BL(2) connected to block 1 and block 2); and
the control circuit is configured to perform the sensing process by determining an average of current in the first bit line and current in the one or more other bit lines while the first bit line and the one or more other bit lines are concurrently receiving current from non-volatile memory cells in multiple blocks (Fig. 3, see also page 7, par. 0094).
Since Lue, Kobayashi and Mokhlesi are from the same field of endeavor, the teachings described by Lue would have been recognized in the pertinent art of Mokhlesi in combination with Kobayashi.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lue with the teachings of Mokhlesi in combination with Kobayashi for the purpose of large-scale computation, see Lue’s page 4, par. 0056.
Regarding claim 9, Mokhlesi in combination with Kobayashi teaches the limitations with respect to claim 1.
Furthermore, Mokhlesi teaches the non-volatile memory cells are positioned on NAND strings (Fig. 5A); and the NAND string are grouped into a plurality of blocks (see pages 5-6, par. 0082-0083).
However, the combination is silent with respect to each of the bit lines of the plurality of bit lines are connected to non-volatile memory cells in every block of the plurality of blocks; and the control circuit is configured to perform the sensing process by determining an average of current in the first bit line and current in the one or more other bit lines while the first bit line and the one or more other bit lines are concurrently receiving current from NAND strings in multiple blocks.
Lue teaches each of the bit lines of the plurality of bit lines are connected to non-volatile memory cells in every block of the plurality of blocks (Fig. 3: BL(1) and BL(2) connected to block 1 and block 2); and
the control circuit is configured to perform the sensing process by determining an average of current in the first bit line and current in the one or more other bit lines while the first bit line and the one or more other bit lines are concurrently receiving current from non-volatile memory cells in multiple blocks (Fig. 3, see also page 7, par. 0094).
Since Lue, Kobayashi and Mokhlesi are from the same field of endeavor, the teachings described by Lue would have been recognized in the pertinent art of Mokhlesi in combination with Kobayashi.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lue with the teachings of Mokhlesi in combination with Kobayashi for the purpose of large-scale computation, see Lue’s page 4, par. 0056.
Allowable Subject Matter
Claims 6-7 and 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 6, there is no teaching or suggestion in the prior art of record to provide the recited non-volatile memory cells connected to the first bit line of the plurality of bit lines are configured to store weight information that is redundant of weight information stored in memory cells connected to one or more other bit lines of the plurality of bit lines; and the control circuit is configured to perform vector-matrix multiplication using the weight information and the sensing process by applying one or more read enable voltages to the non-volatile memory cells and sensing current concurrently flowing in the first bit line and the one or more other bit lines including determining average of current concurrently flowing on the first bit line and on the one or more other bit lines.
With respect to claim 7, there is no teaching or suggestion in the prior art of record to provide the recited non-volatile memory cells are positioned on NAND strings; the NAND strings include select gates; the non-volatile memory cells are configured to be programmed into a set of data states defined by current distributions when applying a common voltage to the non-volatile memory cells; the non-volatile storage apparatus further comprises a plurality of select lines connected to the select gates and the control circuit; memory cells connected to the first bit line of the plurality of bit lines are configured to store weight information that is redundant of weight information stored in memory cells connected to one or more other bit lines of the plurality of bit lines; the control circuit is configured to perform vector-matrix multiplication using the weight information and the sensing process by: applying an input vector to the select lines, and sensing output current from the bit lines including determining average of current flowing on the first bit line and on the one or more other bit lines while the first bit line and on the one or more other bit lines in response to the input vector.
With respect to claim 10, there is no teaching or suggestion in the prior art of record to provide the recited non-volatile memory cells are grouped into a plurality of blocks; each of the bit lines of the plurality of bit lines are connected to non-volatile memory cells in every block of the plurality of blocks; non-volatile memory cells connected to the first bit line of the plurality of bit lines are configured to store weight information that is redundant of weight information stored in non-volatile memory cells connected to one or more other bit lines of the plurality of bit lines; and the control circuit is configured to perform vector-matrix multiplication using the weight information and the sensing process by determining an average of current in the first bit line and current in the one or more other bit lines while the first bit line and the one or more other bit lines are concurrently receiving current from non-volatile memory cells in multiple blocks.
With respect to claim 11, there is no teaching or suggestion in the prior art of record to provide the recited non-volatile memory cells are positioned on NAND strings; the NAND strings include select gates; the NAND strings are grouped into a plurality of blocks; the non-volatile memory cells are configured to be programmed into a set of data states defined by current distributions when applying a common voltage to the non-volatile memory cells; the non-volatile storage apparatus further comprises a plurality of word lines connected to the non-volatile memory cells and the control circuit; the non-volatile storage apparatus further comprises a plurality of select lines connected to the select gates and the control circuit; each of the bit lines are connected to NAND strings in every block of the plurality of blocks; memory cells connected to the first bit line of the plurality of bit lines are configured to store weight information that is redundant of weight information stored in memory cells connected to one or more other bit lines of the plurality of bit lines; and the control circuit is configured to perform vector-matrix multiplication using the weight information and the sensing process by: applying read enable voltages to the word lines, applying an input vector to the select lines while applying the read enable voltages to the word lines, and sensing an output from the bit lines including determining average of current flowing on the first bit line and on the one or more other bit lines while the first bit line and the one or more other bit lines are concurrently receiving current from NAND strings in multiple blocks in response to the input vector.
Claims 14-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 14, there is no teaching or suggestion in the prior art of record to provide the recited steps of storing same weight information redundantly in non-volatile memory cells connected to different bit lines of a predetermined groups of bit lines, and performing vector-matrix multiplication using the weight information, comprising applying one o more read enable voltages to the non-volatile memory cells, in combination with the other limitations.
With respect to independent claim 18, there is no teaching or suggestion in the prior art of record to provide the recited memory cells connected to a first bit line of a respective predetermined group of bit lines are configured to store weight information that is redundant of weight information stored in memory cells connected to one or more other bit lines of the respective predetermined group of bit lines, the control circuit is configured to perform vector-matrix multiplication by applying an input vector to the select lines while applying the read enable voltages to the word lines, and sensing an output from the bit lines using the senses amplifiers including determining average of current flowing on multiple bit lines within the predetermined groups of bit lines while the multiple bit lines are concurrently receiving current from NAND strings in multiple blocks in response to the input vector, in combination with the other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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