Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant's election with traverse of Group I, Species I (Fig. 3) claims 1-6 in the reply filed on 08/20/2026 is acknowledged. The traversal is on the ground(s) that search and examination of the species I and II can be made without serious burden. This is not found persuasive because the species require a different field of search (e.g., searching different subclasses or electronic resources or non patent language, or deploying different search queries); and/or the prior art applicable to one species would not likely be applicable to another species; and/or the species are likely to raise different non-prior art issues under U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Claims 4-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 08/20/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-3 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 defines in lines 4, 7 “the semiconductor substrate” has antecedent issues.
Claim 1 defines in line 6 “the temperature” has antecedent issues.
Claim 1 defines in line 4 “the order of the lot” has antecedent issues.
Claim 1 defines “the order of the lot” is indefinite as it is not clear wat it means. Is it refer to how many lots of semiconductor substrates or number of substrates in a single lot. Appropriate correction is required.
Claim 1 defines ” in the predetermined lot range” is not clear what it refers to. Appropriate correction is required.
Claim 2 defines “an abnormality” has antecedent issues” which should be “the abnormality”.
Claims 2-3 are also rejected being dependent on rejected claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 are rejected under 35 U.S.C. 103 as being obvious over Hunter et al (US 2006/0086713 A1) in view of JP 2007507889 A (herein after ‘’7889)
Regarding claim 1: Hunter teaches in Fig. 1 about a heat treatment apparatus that continuously performs heat treatment on a plurality of semiconductor substrates on a lot basis, the heat treatment apparatus comprising:
PNG
media_image1.png
630
872
media_image1.png
Greyscale
a plurality of lamps 46 that heats the semiconductor substrate 32;
a power source [0055] that supplies a lamp voltage to the plurality of lamps;
a temperature detector 70 that detects the temperature of the semiconductor substrate; and
a controller 76 that controls the lamp voltage or a lamp current applied to the plurality of lamps and detects an abnormality in the heat treatment apparatus,
wherein
the controller controls the lamp voltage or the lamp current applied to the plurality of lamps based on the temperature of the semiconductor substrate detected by the temperature detector [0010], when n is a positive integer of 2 or more indicating the order of the lot of the semiconductor substrate to be treated, the controller calculates a difference effect size (n), based on a maximum lamp voltage or a maximum lamp current applied to the plurality of lamps, according to an equation below: Difference effect size (n) = (maximum lamp voltage or maximum lamp current (n) – maximum lamp voltage or maximum lamp current (n-1))/standard deviation of the maximum lamp voltage or maximum lamp current in the predetermined lot range, and the controller determines that an abnormality has occurred when the difference effect size (n) exceeds a first threshold.
Hunter does not explicitly talk about when n is a positive integer of 2 or more indicating the order of the lot of the semiconductor substrate to be treated, the controller calculates a difference effect size (n), based on a maximum lamp voltage or a maximum lamp current applied to the plurality of lamps, according to an equation below: Difference effect size (n) = (maximum lamp voltage or maximum lamp current (n) – maximum lamp voltage or maximum lamp current (n-1))/standard deviation of the maximum lamp voltage or maximum lamp current in the predetermined lot range, and the controller determines that an abnormality has occurred when the difference effect size (n) exceeds a first threshold.
‘7889 teaches in abstract and Fig. 12 about for determining failure of a process performed by a semiconductor processing tool (therefore abnormality detection) and the results can then be used to adjust the process recipe for the current or next substrate lot (therefore when n is a positive integer of 2 or more indicating the order of the lot of the semiconductor substrate to be treated) and a failure can be predicted to occur when the difference between the actual result and the simulated result (or variance, root mean square, or other statistic) exceeds a predetermined threshold (therefore the first threshold). The predetermined threshold may include, for example, a fraction of the average value for a particular data, ie, 5%, 10%, 15%, or a multiple of the root mean square of the data, ie 1σ, 2σ, and 3σ. Once a failure is detected and the data remaining in the column of the matrix can be normalized by the standard deviation of the data in the column.
Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to have the equation as claimed as a simulation profile from the process for detecting a failure and controlling a process executed by a semiconductor processing in Hunter’s apparatus according to the teachings of ‘7889 using mathematical modeling/calculation.
Regarding claim 3: Hunter in view of ‘7889 does not explicitly talk about wherein the first threshold is 1.2 or more and 3.0 or less.
However ‘7889 teaches about a failure can be predicted to occur when the difference between the actual result and the simulated result (or variance, root mean square, or other statistic) exceeds a predetermined threshold (therefore the first threshold) and the predetermined threshold may include, for example, a fraction of the average value for a particular data, ie, 5%, 10%, 15%, or a multiple of the root mean square of the data, ie 1σ, 2σ, and 3σ.
Thus, it would have been obvious to one of the ordinary skill in the art at the time the application was filed to have the feature as claimed with routine experiment and optimization since the threshold value is critical in order to predict a failure according to the teaching of ‘7889 . In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Claim 2 is rejected under 35 U.S.C. 103 as being obvious over Hunter et al (US 2006/0086713 A1) in view of JP 2007507889 A (herein after ‘’7889) and further in view of Li et al. (CN 115241087 A)
Regarding claim 2: Hunter in view of ‘7889 does not explicitly talk about further comprising a warning unit that issues a warning about an abnormality in the heat treatment apparatus through a display or a voice, wherein when the controller determines that an abnormality has occurred, the warning unit issues a warning.
Li teaches in Fig. 3 about a warning unit 305 that issues a warning about an abnormality in the heat treatment apparatus through a display or a voice, wherein when the controller determines that an abnormality has occurred, the warning unit issues a warning (by setting the alarm unit 305, the technical cavity heat treatment process self-cleaning system of this embodiment can be the to-be-processed batch wafer to be processed from the cleaning program to the station, and the self-cleaning program does not reach the cleaning effect, sending alarm information to the related engineering personnel. The related engineering personnel, such as technical engineers and equipment engineers, can monitor the temperature change curve in real time in the heat treatment process needed to be concerned, so as to judge whether it is necessary to introduce the self-cleaning program and even if necessary to maintain the device. and in the fake sheet process after the self-cleaning program is executed, if the temperature change curve shows that the side product on the temperature measuring probe may not be removed by the self-cleaning program, then the alarm unit 305 will also alarm to the related engineering staff in time, so as to timely process the device abnormality).
Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to have the feature as claimed in Hunter’s apparatus according to the teachings of Li so as to timely process the device abnormality.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
Prosecution Insights