DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US-20190393320-A1; Yoo) in view of Moon et al. (US-20220173107-A1; Moon) and further in view of Liu et al. (US-20200006545-A1; Liu).
Regarding claim 1, Yoo discloses a semiconductor device comprising: an active region (Fig. 1A, ACT; ¶33) disposed in a substrate (Fig. 1A, 10; ¶33); a device isolation layer (Fig. 1A, ISO; ¶33) defining the active region; a gate structure (Fig. 1A, 70; ¶33) disposed in the substrate and extending in a first horizontal direction (into the page) to cross the active region; bit line structures (Fig. 1A, 80; ¶47) crossing the gate structure and extending in a second horizontal direction, intersecting the first horizontal direction; and a contact plug (Fig. 1A, 81; ¶47) disposed between the bit line structures, wherein the active region includes a first source/drain region (Fig. 1A, 15; ¶33), a second source/drain region (Fig. 1A, 15; ¶47 upper half), and a channel region (not labeled approximate to gate), the first source/drain region and the second source/drain region are spaced apart from each other by the gate structure, the first source/drain region includes a first lower region and a first upper region on the first lower region,… , and the contact plug (Fig. 1A, 91 or 81; ¶47/49) contacts the first upper region of the first source/drain region.
Yoo is silent on the relative direction the gate structure and the bit line; the first lower region is a first crystal region, the first upper region is a second crystal region, different from the first crystal region,
Moon discloses a semiconductor device comprising a gate structure (Fig. 1, WL) extending in a first direction (X2) and a Bit line (BL) extending in a second direction (X3)
It is common in the art to have a gate line (word line) extending in a first direction and a bit line extending in a second direction when forming high speed low voltage memory devices .
Liu discloses forming a source/drain structure (Fig. 6, 292; ¶21) comprising a first upper region (Fig. 6, 213/219; ¶21,39 re-crystalized) is a second crystal region where the first lower region (Fig. 6, 217; ¶21) is a first crystal region, the first upper region
Therefore, before the effective filing date it would have been obvious to one having ordinary skill in the art to use this configuration to form a standard memory device that functions at high speed and relatively low voltage, to have source/drain regions with; to use the source/drain configuration of Liu to achieve a high surface concentration (surface pile up) dopant profile.
Regarding claim 2, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, but is silent on wherein a content of a first element in the first upper region is greater than a content of the first element in the first lower region, and the first element includes at least one of carbon (C), silicon (Si), and germanium (Ge).
Liu discloses a source/drain structure comprising a first upper region (Fig. 6, 213/2219; ¶21) is greater than a content of the first element in the first lower region (Fig. 6, 217; ¶21), and the first element includes at least one of carbon (C), silicon (Si), and germanium (Ge).(¶17)
Regarding claim 3, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, wherein the first upper region (Fig. 6, 213/2219; ¶21 Liu) further includes an N-type impurity, and the first lower region (Fig. 6, 217; ¶21 Liu) includes an N-type impurity.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to use the source/drain configuration of Liu to achieve a high surface concentration (surface pile up) dopant profile.
Regarding claim 4, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, wherein the first lower region (Fig. 6, 217; ¶21 Liu) has an etch selectivity with the first upper region. (Fig. 6, 213/2219; ¶21 Liu)
Before the effective filing date it would have been obvious to one having ordinary skill in the art to use the source/drain configuration of Liu to achieve a high surface concentration (surface pile up) dopant profile.
Regarding claim 5, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, wherein the first crystal region is a first single crystal region, (Fig. 6, 217; ¶21 Liu) and the second crystal region is a recrystallized region. (Fig. 6, 213/2219; ¶21,39 re-crystalized Liu)
Before the effective filing date it would have been obvious to one having ordinary skill in the art to use the source/drain configuration of Liu to achieve a high surface concentration (surface pile up) dopant profile.
Regarding claim 6, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, wherein the channel region (Fig. 1A, ACT; ¶33,36 Yoo) has a single crystal structure having a P-type conductivity, the first crystal region has a single crystal structure having an N-type conductivity(Fig. 1A, 15; ¶33,36 lower half Yoo), and the second crystal region (Fig. 1A, 15; ¶33,36 upper half Yoo)
has a recrystallized structure having an N-type conductivity.
Regarding claim 7, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, wherein the contact plug (Fig. 1A, 90 ; ¶47/49) includes a lower portion (Fig. 1A, 91; ¶47/49) disposed in the substrate (Fig. 1A, 10; ¶33) and contacting the first source/drain region (Fig. 1A, 15; ¶33,36 Yoo) and an upper portion (Fig. 1A, right pillar 91; ¶47/49) disposed on the substrate, and a horizontal width of the lower portion is greater than a horizontal width of the upper portion.
Regarding claim 8, Yoo in view of Moon Liu discloses the semiconductor device of claim 7, wherein the lower portion (Fig. 1A, 90 ; ¶47/49) protrudes in a horizontal direction toward (end portions) the first source/drain region. (Fig. 1A, 15; ¶33,36 Yoo)
Regarding claim 9, Yoo in view of Moon Liu discloses the semiconductor device of claim 7, but is silent on wherein a vertical thickness of the lower portion of the contact plug is less than a vertical thickness of the first upper region.
Change is shape or size
This is simple change in the size or proportion of the plug.
Therefore it would have been obvious to one having ordinary skill in the art to make the lower portion of the plug shorter to reduce the overall device size, and where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Regarding claim 10, Yoo in view of Moon Liu discloses the semiconductor device of claim 7, wherein the lower portion (Fig. 1A, 90 ; ¶47/49) of the contact plug is spaced apart from the first lower region. (Fig. 1A, 15; ¶33,36 lower half Yoo)
Regarding claim 11, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, but is silent on wherein a vertical thickness of the first upper region is about 20 nm to about 30 nm.
However, the applicant has not presented persuasive evidence in the specification that the claimed dimensions are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed dimensions). Also, the applicant has not shown that the claimed dimensions produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Therefore, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to achieve the optimal vertical thickness of the second region through routine experimentation. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05 (II)
Regarding claim 12, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, wherein the contact plug includes doped polysilicon. (Fig. 1A, 90; ¶49 Yoo)
Regarding claim 13, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, wherein the second source/drain region (Fig. 1A, a second 15; ¶33,36 Yoo) includes a second lower region (Fig. 1A, a second 15; ¶33,36 lower half Yoo) and a second upper region (Fig. 1A, a second 15; ¶33,36 upper half Yoo) on the second lower region, and the second upper region includes a material the same as a material of the first upper (Fig. 1A, 15; ¶33,36 upper half Yoo)
region and contacts (physically & electrically) a lower end of one of the bit line structures.(Fig. 1A, 80; ¶33 Yoo)
Regarding claim 14, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, wherein the second source/drain region (Fig. 1A, a second 15; ¶33,36 Yoo)
includes a second lower region (Fig. 1A, a second 15; ¶33,36 lower half Yoo) , and the second lower region includes a material the same as a material of the first lower region (Fig. 1A, 15; ¶33,36 lower half Yoo) and contacts (electrically) a lower end of one of the bit line structures.(Fig. 1A, 80; ¶33 Yoo)
Regarding claim 15, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, wherein the gate structure (Fig. 1A, 70; ¶33) is disposed between the first source/drain region (Fig. 1A, 15; ¶33,36 Yoo) and the second source/drain region.(Fig. 1A, a second 15; ¶33,36 Yoo)
Regarding claim 16, Yoo in view of Moon Liu discloses the semiconductor device of claim 1, wherein the gate structure (Fig. 1A, 70; ¶33 Yoo) is formed in the substrate (Fig. 1A, 10; ¶33 Yoo) and disposed in a gate trench extending in the first horizontal direction, and includes a gate dielectric layer (Fig. 1A, 20; ¶52 Yoo) covering an inner wall of the gate trench, a gate electrode (Fig. 1A, 30; ¶52 Yoo) on the gate dielectric layer, and a gate capping layer (Fig. 1A, 65; ¶52 Yoo) on the gate electrode.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US-20220115377-A1; Kim) in view of Moon et al. (US-20220173107-A1; Moon) and further in view of Liu et al. (US-20200006545-A1; Liu).
Regarding claim 17, Kim discloses a semiconductor device comprising: an active region (Fig. 1,104; ¶17) disposed in a substrate (Fig. 1,100; ¶17) ; a device isolation layer (Fig. 1,106a; ¶16) defining the active region; a gate structure (Fig. 1,128; ¶14) disposed in the substrate and extending in a first horizontal direction (Fig. 2,D1; ¶13) to cross the active region; bit line structures (Fig. 1,158; ¶14) crossing the gate structure and extending in a second horizontal direction (Fig. 2,D2; ¶13) , intersecting the first horizontal direction; and a contact plug (Fig. 1,146A; ¶24) disposed between the bit line structures, wherein the active region includes a first source/drain region (Fig. 1, 129; ¶21), a second source/drain region (Fig. 1, second 129; ¶21), and a channel region (not labeled approximate to gate), the first source/drain region and the second source/drain region are spaced apart from each other by the gate structure (Fig.1, by gate structures and isolation), the first source/drain region includes a first lower region (Fig. 1, lower half 129; ¶21) and a first upper region (Fig. 1, upper half 129; ¶21) on the first lower region, the substrate includes a contact hole (Fig. 1,location of 146) formed between the bit line structures and exposing the first upper region and the device isolation layer, a portion of the contact plug (Fig. 1,146A; ¶24) is disposed in the contact hole and contacts the first upper region, but is silent on the first lower region has a first etch selectivity with respect to the device isolation layer, and the first upper region has a second etch selectivity higher than the first etch selectivity with respect to the device isolation layer.
Liu discloses forming a source/drain structure (Fig. 6, 292; ¶21) comprising a first upper region (Fig. 6, 213/219; ¶21,39 re-crystalized) is a second crystal region where the first lower region (Fig. 6, 217; ¶21) is a first crystal region, the first upper region is a second crystal region, different from the first crystal region, The different crystal regions represent different etch selectivity relative to the isolation layer.
Therefore, before the effective filing date it would have been obvious to one having ordinary skill in the art to have source/drain regions with; to use the source/drain configuration of Liu to achieve a high surface concentration (surface pile up) dopant profile.
Regarding claim 18, Kim in view of Liu discloses the semiconductor device of claim 17, wherein the contact plug (Fig. 1,146A; ¶24 Kim) includes a lower portion (Fig. 1,144a; ¶84 Kim) disposed in the contact hole and contacting the first upper region (Fig. 1, upper half 129; ¶21 Kim), and an upper portion (Fig. 1,136a; ¶84 Kim) disposed on the substrate. (Fig. 1,100; ¶17 Kim)
Regarding claim 20, Kim a semiconductor device comprising: an active region(Fig. 1,104; ¶17) disposed in a substrate (Fig. 1,100; ¶17); a device isolation layer (Fig. 1,106a; ¶16) defining the active region; a gate structure (Fig. 1,128; ¶14) formed in the substrate and disposed in a gate trench extending in a first horizontal direction (Fig. 2,D1; ¶13) to cross the active region; bit line structures (Fig. 1,158; ¶14) crossing the gate structure and extending in a second horizontal direction (Fig. 2,D2; ¶13), intersecting the first horizontal direction; a contact plug (Fig. 1,146A; ¶24) disposed between the bit line structures; a landing pad (Fig. 1,166; ¶40) on the contact plug; and capacitor structure (Fig. 1, 170; ¶41) on the landing pad, wherein the active region includes a first source/drain region (Fig. 1, 129; ¶21), a second source/drain region (Fig. 1, second 129; ¶21), and a channel region (not labeled approximate to gate), the first source/drain region and the second source/drain region are spaced apart from each other by the gate structure (Fig.1, by gate structures and isolation), the first source/drain region includes a first lower region (Fig. 1, lower half 129; ¶21) and a first upper region (Fig. 1, upper half 129; ¶21) on the first lower region,…and the first upper region of the first source/drain region is in contact with the device isolation layer, the contact plug, and the gate structure.
Kim is silent on the first lower region is a first crystal region, the first upper region is a second crystal region, different from the first crystal region,
Liu discloses forming a source/drain structure (Fig. 6, 292; ¶21) comprising a first upper region (Fig. 6, 213/219; ¶21,39 re-crystalized) is a second crystal region where the first lower region (Fig. 6, 217; ¶21) is a first crystal region, the first upper region is a second crystal region, different from the first crystal region.
Therefore, before the effective filing date it would have been obvious to one having ordinary skill in the art to have source/drain regions with; to use the source/drain configuration of Liu to achieve a high surface concentration (surface pile up) dopant profile.
Allowable Subject Matter
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 19, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the first upper region is in contact with side surfaces and a lower surface of the lower portion of the contact plug.”, as recited in Claim 19, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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