Response to Arguments
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 22 is objected to because of the following informalities: - Claim 22 is currently dependent on cancelled claim 10. Based on the content of the claim, it appears that the claim was intended to be dependent on claim 21. Search and consideration of the application will be based on this assumption Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claims 17 and 22, the recitation of “formed only in at least one portion between the heat sink and the circuit carrier.” “Only” indicates exclusive positioning while “at least” indicates a minimum of positions and contradicts the previous recitation of “only.” For the sake of prosecution, the claim will be interpreted to allow for additional portions to be allowed but only if the position of “between the heat sink and the circuit carrier” is also met.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12-13, 17-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Viswanathan et al. (U.S. Publication No. 2018/0153030 A1; hereinafter Viswanathan)
With respect to claim 12, Viswanathan discloses a production method for producing a power module [10] having a heat sink [18] using a sintering process, the method comprising: applying a specific sintering pressure (See ¶[0011]), using a sintering stamp (see ¶[0023]), to an arrangement including the heat sink, a sintered connection layer [16] applied to the heat sink, and a circuit carrier [12] applied to the sintered connection layer (See Figure 1).
With respect to claim 13, Viswanathan discloses wherein at least one power semiconductor and/or at least one electrical contact element and/or at least one casting compound and/or at least one further sintered connection layer [38], are applied to the circuit carrier before the sintering pressure is applied by the sintering stamp (See ¶[0020] and ¶[0023]).
With respect to claim 17, Viswanathan discloses wherein the sintered connection layer is formed only in at least one portion between the heat sink and the circuit carrier, which portion is configured for thermal bonding of the circuit carrier and power module components applied or to be applied there to the circuit carrier, wherein at least one portion of another layer including a solder connection layer, is also formed between the heat sink and the circuit carrier (See Figure 1).
With respect to claim 18, Viswanathan discloses wherein the specific sintering pressure and/or a specific hydrostatic pressure is in a range from 5 MPa to 30 MPa (See ¶[0028]).
With respect to claim 19, Viswanathan discloses wherein the heat sink has a noble metal coating on a side to which the sintered connection layer is applied (See ¶[0016]).
With respect to claim 20, Viswanathan discloses wherein: (i) the sintered connection layer includes silver and/or copper, and/or (ii) the sintered connection layer has an average layer thickness in a range from 50 μm to 200 μm (see ¶[0024]).
With respect to claim 21, Viswanathan discloses a power module [10] which is produced by applying a specific sintering pressure, using a sintering stamp, to an arrangement including the heat sink [18], a sintered connection layer [16] applied to the heat sink, and a circuit carrier [12] applied to the sintered connection layer (Examiner Note: The claim is structured as a product-by-process claim. Please note that "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)).
With respect to claim 22, Viswanathan discloses wherein the power module comprises the heat sink, the sintered connection layer applied to the heat sink, and the circuit carrier applied to the sintered connection layer (see Figure 1), wherein the sintered connection layer is formed only in at least one portion between the heat sink and the circuit carrier, which is configured for thermal bonding of the circuit carrier and power module components applied or to be applied thereto, wherein at least a portion of another layer including a solder connection layer [38] is also formed between the heat sink and the circuit carrier (See ¶[0020] and ¶[0023]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Viswanathan in view of Bayerer (U.S. Publication No. 2013/0040424 A1)
With respect to claim 14, Viswanathan fails to disclose wherein the sintering stamp has a cavity that can be filled with a hydrostatic medium, wherein the sintering stamp is placed on the heat sink and/or the circuit carrier in such a way that the sintered connection layer are accommodated in the cavity, wherein the cavity is closed by the heat sink and/or by the circuit carrier, wherein the specific sintering pressure is exerted on the arrangement by filling the cavity with the hydrostatic medium at a specific hydrostatic pressure, and wherein the hydrostatic medium is heated to a specific sintering temperature. In the same field of endeavor, Bayerer teaches the sintering stamp has a cavity that can be filled with a hydrostatic medium, wherein the sintering stamp is placed on the heat sink and/or the circuit carrier in such a way that the sintered connection layer are accommodated in the cavity, wherein the cavity is closed by the heat sink and/or by the circuit carrier, wherein the specific sintering pressure is exerted on the arrangement by filling the cavity with the hydrostatic medium at a specific hydrostatic pressure, and wherein the hydrostatic medium is heated to a specific sintering temperature (See ¶[0002] and ¶[0025]). Implementation of a hydrostatic sintering stamp as taught by Bayerer allows for adaptation to the topology of the structures being joined and seals against contamination or pressurized gas during the attachment process (See Bayerer ¶[0025]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 15, Viswanathan fails to disclose wherein the sintering stamp includes a stamp portion having a topography which is adapted to a topography of the circuit carrier and the sintered connection layer, and wherein the stamp portion is heated to a specific sintering temperature. In the same field of endeavor, Bayerer teaches wherein the sintering stamp includes a stamp portion having a topography which is adapted to a topography of the circuit carrier and the sintered connection layer, and wherein the stamp portion is heated to a specific sintering temperature. (See ¶[0002] and ¶[0025]). Implementation of the sintering stamp as taught by Bayerer allows for adaptation to the topology of the structures being joined and seals against contamination or pressurized gas during the attachment process (See Bayerer ¶[0025]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 16, Viswanathan fails to disclose wherein the sintering stamp has a flat stamp surface or a flat stamp portion, wherein: (i) the circuit carrier is free of power module components before and/or during the application of the sintering pressure by the sintering stamp, or (ii) power module components are already applied to the circuit carrier before the application of the sintering pressure by the sintering stamp, which components have an at least substantially flat, topology or topography, and wherein the flat stamp surface or the flat stamp portion is heated to a specific sintering temperature.
In the same field of endeavor, Bayerer teaches the sintering stamp has a flat stamp surface or a flat stamp portion (See Figure 2), wherein: (i) the circuit carrier is free of power module components before and/or during the application of the sintering pressure by the sintering stamp, or (ii) power module components are already applied to the circuit carrier before the application of the sintering pressure by the sintering stamp, which components have an at least substantially flat, topology or topography, and wherein the flat stamp surface or the flat stamp portion is heated to a specific sintering temperature (See Figure 12 and ¶[0002] and ¶[0025]).
Implementation of the sintering stamp as taught by Bayerer allows for adaptation to the topology, including flat stamping portions, of the structures being joined and seals against contamination or pressurized gas during the attachment process (See Bayerer ¶[0025]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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