DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This action is responsive to the following communications: the application filed May 14, 2024 and the Information Disclosure Statement (IDS) filed May 14, 2024.
Claim 1 is pending in the application. Claim 1 is an independent claim.
Information Disclosure Statement
Acknowledgement is made of Applicant’s IDS submitted on May 14, 2024. The IDS submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as anticipated by U.S. Published Patent Application No. 20200152692 A1 to Liao (referred to hereafter as “Liao”).
Regarding claim 1, Liao teaches a stacked light emitting device {Figure 19}, comprising: a first LED stack {30c}; a second LED stack {30b} disposed under the first LED stack; a third LED stack {30a} disposed under the second LED stack; each of the first, second, and third LED stacks has a light generation region {the regions under 301c and covered by the right connector to the right pad and the left connector to the left pad of each stack} and a peripheral region {the regions under 302c and covered by the right connector to the right pad and the left connector to the left pad of each stack} disposed around the light generation region {the regions under 301c and covered by the right connector to the right pad and the left connector to the left pad of each stack }; a plurality of pads {301c, 302c} disposed over the first LED stack {30c}; and a third-1 connector {the left connector to the 30a left pad} and a third-2 connector {the right connector to the 30a right pad} disposed between the second LED stack and the third LED stack 7} and a second conductivity type semiconductor layer {N; see Figure 7} of the light generation region of the third LED stack {the connectors connect to the top and bottom semiconductor layers of 30a}, respectively, and the third-1 connector {the left connector to the 30a left pad}, the third-2 connector, or both cover a side surface of the peripheral region of the third LED stack {the right connector to the 30a right pad covers a side surface of the region under 302c}.
Nonstatutory Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,002,912 B2 to Lee et al. (referred to hereafter as “Lee”). Although the claims at issue are not identical, they are not patentably distinct from each other because of the following:
Regarding claim 1, Lee claim 1 includes a stacked light emitting device, comprising: a first LED stack; a second LED stack disposed under the first LED stack; a third LED stack disposed under the second LED stack; each of the first, second, and third LED stacks has a light generation region and a peripheral region disposed around the light generation region; a plurality of pads disposed over the first LED stack; and a third-1 connector and a third-2 connector disposed between the second LED stack and the third LED stack, wherein: the third-1 connector and the third-2 connector are electrically connected to a first conductivity type semiconductor layer and a second conductivity type semiconductor layer of the light generation region of the third LED stack, respectively, and the third-1 connector, the third-2 connector, or both cover a side surface of the peripheral region of the third LED stack {excerpt of Lee claim 1: “A stacked light emitting device, comprising: a first LED stack; a second LED stack disposed under the first LED stack; a third LED stack disposed under the second LED stack; each of the first LED stack, the second LED stack, and the third LED stack has a light generation region and a peripheral region disposed around the light generation region; a plurality of pads disposed over the first LED stack; and a third-1 connector and a third-2 connector disposed on the third LED stack, wherein: the third-1 connector and the third-2 connector are electrically connected to a first conductivity type semiconductor layer and a second conductivity type semiconductor layer of the light generation region of the third LED stack, respectively, and the third-1 connector, the third-2 connector, or both cover a side surface of the peripheral region of the third LED stack…}.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert Carpenter whose telephone number is (571)270-5140. The examiner can normally be reached on Monday through Friday from 9AM to 5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Robert K Carpenter/Primary Examiner, Art Unit 2812
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