DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on May 14, 2024 was considered by the Examiner.
Election/Restrictions
Applicant's election Species J with claims 1 and 6 readable thereon in the reply filed on July 6, 2026 is acknowledged. Accordingly, claims 2-5 and 7-20 are withdrawn from consideration. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). As the election was made without traverse, the requirement is deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US20080157329A1 (“Inoue”).
RE: Claim 1, Inoue discloses A module (100 in FIG. 1) comprising:
a first electronic component (30, [0034]) having a first component surface (bottom surface of 30) and a second component surface (top surface of 30) facing away from each other, the first electronic component including a first connection terminal (32 or 36, [0036]) at the first component surface for face bonding (The first semiconductor element 30 is connected to the connection pads 12B of the wiring substrate 10 via bumps 36 such as solder bumps, gold bumps, or the like, which are joined to electrode surfaces 32, by flip-chip bonding, [0036]);
a second electronic component (60, [0034]) having a third component surface (bottom surface of 60) and a fourth component surface (top surface of 60) facing away from each other, the second electronic component including a second connection terminal (62, [0044]) at the fourth component surface for wire bonding (the electrodes 62 and the wire bonding connection pads 22B can be connected easily by the bonding wires 70, [0045]);
a first substrate (10, [0034]) having a first substrate surface (bottom surface of 10) and a second substrate surface (top surface of 10) facing away from each other; and
a second substrate (20, [0034]) having a third substrate surface (bottom surface of 20) and a fourth substrate surface (top surface of 20) facing away from each other, the second substrate having an opening (24, [0038]),
the second substrate being disposed such that the second substrate overlaps the first substrate with the third substrate surface (bottom surface of 20) facing the first substrate while the second substrate is spaced from the first substrate on a side of the second substrate surface (top side of top surface of 10) of the first substrate (FIG. 1 shows the second substrate 20 overlaps the first substrate 10 with the bottom surface of 20 facing the first substrate 10 while the second substrate 20 is spaced from the first substrate 10 on a top side of the top surface of the first substrate 10),
the first substrate and the second substrate being electrically connected to each other (the wiring substrate 10 and the wiring substrate 20 are connected electrically by solder balls 40, [0034]),
the first electronic component and the second electronic component being disposed such that the second component surface (top surface of 30) and the third component surface (bottom surface of 60) face each other (FIG. 1 shows top surface of 30 and bottom surface of 60 face each other),
at least a portion of the second electronic component being disposed inside the opening (FIG. 1 shows at least a portion of 60 is disposed inside opening 24 of 20),
the first electronic component being mounted on the second substrate surface by face bonding using the first connection terminal (The first semiconductor element 30 is connected to the connection pads 12B of the wiring substrate 10 via bumps 36 such as solder bumps, gold bumps, or the like, which are joined to electrode surfaces 32, by flip-chip bonding, [0036]; FIG. 1 shows 30 being mounted on top surface of 10 by face bonding using 32 or 36),
the second electronic component being wire-bonded to the fourth substrate surface (top surface of 20) using the second connection terminal in a position in which the third component surface (bottom surface of 60) is directed toward the second substrate surface (top surface of 10; the electrodes 62 and the wire bonding connection pads 22B can be connected easily by the bonding wires 70, [0045]; FIG. 1 shows 60 being wire-bonded to the top surface of 20 using 62 in a position in which the bottom surface of 60 is directed toward the top surface of 10).
RE: Claim 6, Inoue discloses The module according to claim 1, wherein the second component surface and the third component surface are spaced from each other and thus fixed relative to each other (The second semiconductor element 60 is joined and supported onto the sealing resin 50 by using the adhesive, [0043]; 60 as the second electronic component is adhered to the surface of the sealing resin in the opening portion 24 by the adhesive, [0053]; 30 is sealed with sealing resin 50, [0042]; FIG. 1 shows the top surface of 30 and the bottom surface of 60 are spaced from each other by a portion of sealing resin 50 and thus fixed relative to each other).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights