DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed March 27, 2026 has been entered. Claims 1-3 and 6-20 remain pending in this application. Claims 4-5 have been cancelled at applicant’s request. Claims 1, 14, and 20 have been amended. No claims have been added. No new matter has been added.
Claim Objections
Claims 1, 8, and 14 objected to because of the following informalities:
Amended Claim 1: ‘Capacitance’ misspelled ‘capacitcance.’
Claim 8: “[T]he second circuit stage is further configured to provided the output signal…” ‘Provided’ is the incorrect tense.
Amended Claim 14: ‘Parasitic’ misspelled ‘parastitic,’ twice.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 and 6-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 11,037,607 B2 to Raymond Chong, et al. (hereafter Chong), in view of US 2023/0023730 A1 to Feng Lin (hereafter Lin) and US 8,085,841 B2 to John F. Bulzacchelli, et al. (hereafter Bulzacchelli).
Regarding Amended Independent Claim 1, Chong discloses an apparatus comprising:
a first circuit stage (A first stage: Chong, Figure 3B) comprising
a current amplifier circuit (The first stage comprising a comparator/amplifier: Chong, Figure 3B) configured to receive
a data input signal (The comparator receiving a data input signal inp: Chong, Figure 3B) and
a second circuit stage (A second circuit stage: Chong, Figure 3B) comprising
a voltage circuit (The second circuit stage being a latch: Chong, Figure 3B)
coupled to the first circuit stage (The second stage coupled to the first stage: Chong, Figure 3B), wherein:
the first circuit stage is configured to
integrate a current (The first circuit stage configured to integrate a current: Chong, Figure 3B)
the second circuit stage is configured to
provide an output signal (The second circuit stage providing an output signal outp and outn: Chong, Figure 3B)
corresponding to a decision (Evaluation of the signal: Chong, col.3:16-17) of a value of the data input signal (The output corresponding to an evaluation of the input signals: Chong, col.7:8-12); and
the apparatus is configured to operate with a double data rate clocking scheme (The apparatus configured to operate with a double data rate (DDR) clocking scheme: Chong, col.11:6-11).
Chong does not expressly disclose the input signal of the first circuit stage incorporating a feedback signal. Lin, however, discloses a circuit as in Claim 1, including a first circuit stage incorporating:
a feedback signal (The comparator receiving a feedback signal: Lin, Figure 5); and
incorporating the signal based on the data input signal and the feedback signal (The input signals being a data input signal DQ and a Feedback signal fb: Lin, Figure 5).
Lin teaches incorporating the decision feedback circuits in the data receiving circuit reduces overall power consumption (Lin, ¶[0015]) and provides more flexible control over the circuit operating state (Lin, ¶[0017]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible, power-efficient feedback mechanism of Lin with the staged circuit architecture of Chong, with a reasonable expectation of success. Both inventions are well known in the field of decision feedback equalization modules and the combination of known inventions with predictable results is obvious and not patentable.
Neither Chong nor Lin disclose integrating currents on parasitic capacitors. Bulzacchelli, however, discloses a Decision Feedback Equalizer (DFE) where the first circuit stage is further configured to:
integrate a first current on a first parasitic capacitance based on a voltage at a first input node (Integrating a first current through Q4 on CH for VOUT- based on the gate voltage at Q4: Bulzacchelli, Figure 8B; Disclosing hold capacitances CH may comprise an on-chip capacitor or inherent parasitic capacitance: Bulzacchelli, col.7:64-67),
integrate a second current on a second parasitic capacitance based on a voltage at a second input node (Integrating a second current through Q3 on CH for VOUT+ based on the gate voltage at Q3: Bulzacchelli, Figure 8B),
integrate a third current on the first parasitic capacitance based on a voltage at a third input node (Integrating a third current through Q7 on CH for VOUT- based on the gate voltage at Q7: Bulzacchelli, Figure 8B), and
integrate a fourth current on the second parasitic capacitance based on a voltage at a fourth input node (Integrating a fourth current through Q6 on CH for VOUT+ based on the gate voltage at Q6: Bulzacchelli, Figure 8B).
Bulzacchelli teaches this configuration, which integrates current on a capacitor, and expressly teaches the use of parasitic capacitance, eliminates settling time requirements for the circuit, making it feasible to increase the number of taps without a significant power penalty (Bulzacchelli, col.2:1-6). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the parasitic capacitance of Bulzacchelli with the stage circuit architecture of Chong, with a reasonable expectation of success. Both inventions are well known in the field of Differential Feedback Equalizers and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2, Chong discloses the apparatus of claim 1, wherein:
the first circuit stage comprises
a first input node (First differential input P: Chong, col.5:17) and
a second input node (Second differential input N: Chong, col.5:17); and
the first circuit stage is further configured to
integrate a first current and a second current (Sampling the inputs: Chong, col.5:17-19)
based on a voltage difference between the first input node and the second input node (Producing a sampled output Inp and Inn: Chong, col.5:22-23).
Regarding Claim 3, Lin discloses the apparatus of claim 1, wherein the first circuit stage is further configured to:
receive a reference signal (Disclosing receiving reference signal Vref: Lin, ¶[0021]); and
integrate a first current and a second current based on a difference between the data input signal and the reference signal (Generating a first and second output signal based on a comparison of data signal DQ and reference signal Vref: Lin, ¶[0021]).
Regarding Claim 6, Chong discloses the apparatus of claim 1, wherein:
the first circuit stage is further configured to
generate a first intermediate output signal (Generating first intermediate output signal Inp: Chong, Figure 1) and
a second intermediate output signal (Generating second intermediate output signal Inn: Chong, Figure 1); and
the second circuit stage is further configured to
provide the output signal (Second circuit stage providing an output signal out: Chong, Figure 1)
based on a difference between the first intermediate output signal and the second intermediate output signal (Output signal out being based on intermediate input signals: Chong, col.7:6-12).
Regarding Claim 7, Chong discloses the apparatus of claim 1, wherein:
the first circuit stage is further configured to
generate a first intermediate output signal (Generating first intermediate output signal Inp: Chong, Figure 1) and
a second intermediate output signal (Generating second intermediate output signal Inn: Chong, Figure 1); and
the second circuit stage is further configured to
provide a first output signal and a second output signal (Generating differential output signals OutP and OutN: Chong, col.7:6-7)
based on the first intermediate output signal and the second intermediate output signal (Output signals out being based on intermediate input signals: Chong, col.7:6-12).
Regarding Claim 8, Chong discloses the apparatus of claim 1, wherein:
the first circuit stage is further configured to
sample the data input signal based on an edge of a first clock signal (Evaluating the data signal on a rising edge of the clock signal: Chong, col.3:16-17); and
the second circuit stage is further configured to
provide the output signal (Providing output signal OutP and OutN: Chong, col.7:6-7)
corresponding to a decision of a value of the sampled data input signal (Output signals out being based on intermediate input signals: Chong, col.7:6-12).
Regarding Claim 9, Chong discloses the apparatus of claim 8, wherein
the first circuit stage and the second circuit stage are
configured to reset (Resetting process: Chong, col.8:26-29)
based on an edge of a second clock signal (The reset process triggered by rise in second clock signal Clkb: Chong, col.8:24-29).
Regarding Claim 10, Chong discloses the apparatus of claim 9, wherein
the second clock signal is an inverted version of the first clock signal (Clock signal Clk and second clock signal Clkb are inverse: Chong, col.8:24).
Regarding Claim 11, Lin discloses the apparatus of claim 1, comprising
a decision feedback equalizer sense amplifier circuit (The circuit including a decision feedback equalizer module: Lin, Figure 1).
Regarding Claim 12, Bulzacchelli discloses the apparatus of Claim 1, further comprising:
a non-volatile memory array coupled to the first circuit stage (A memory array connected to the first stage: Bulzacchelli, col.3:61-67),
wherein data read from the non-volatile memory array comprises the data input signal (Data input signals comprising data from the memory array: Bulzacchelli, col.4:1-12).
Regarding Claim 13, Lin discloses the apparatus of claim 1,wherein
the feedback signal corresponds to a decision of a value of previous data input signal (Output of the final stage includes feedback signal fb input to the first stage: Lin, ¶[0087]).
Claim(s) 14-15 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0023730 A1 to Feng Lin (hereafter Lin) in view of US 2023/0267970 A1 to Jui-Jen Wu, et al. (hereafter Wu) and US 8,085,841 B2 to John F. Bulzacchelli, et al. (hereafter Bulzacchelli).
Regarding Independent Claim 14, Lin discloses a system comprising:
a first decision feedback equalizer sense amplifier circuit (Disclosing a decision feedback equalizer circuit: Lin, Figure 1),
a second decision feedback equalizer sense amplifier circuit (A second decision feedback unit: Lin, Figure 3) comprising
a first input node coupled to the data input signal (A first input receiving a data input signal: Lin, ¶[0035]),
a second input node coupled to the reference signal (A reference signal: Lin, Figure 5),
a third input node coupled to the first output node of the first decision feedback equalizer sense amplifier circuit (A third input including feedback from the first DFE circuit: Lin, ¶[0016]),
a fourth input node coupled to the second output node of the first decision feedback equalizer sense amplifier circuit (A fourth input node coupled to the first DFE: Lin, ¶[0016]),
a first output node coupled to the third input node of the first decision feedback equalizer sense amplifier circuit (The output of the second DFE couple back to the input of the first DFE: Lin, ¶[0039] and Lin, Figure 5) and
a second output node coupled to the fourth input node of the first decision feedback equalizer sense amplifier circuit (The output of the second DFE couple back to the input of the first DFE: Lin, ¶[0039] and Lin, Figure 5)
wherein the first decision feedback equalizer sense amplifier circuit and the second decision feedback equalizer sense amplifier circuit
are configured to operate with a double data rate clocking scheme (The circuits configured to operate with a double data rate clocking scheme: Lin, ¶[0096]).
Lin doesn’t expressly disclose all the same inputs of the first DFE. Wu, however, discloses a circuit as in Claim 14, including a first DFE circuit comprising:
a first input node (First input node V1: Wu, Figure 1)
coupled to a data input signal (Data signals DL and DLB: Wu, ¶[0016]),
a second input node (Second input node V2: Wu, Figure 1)
coupled to a reference signal (Reference signal node: Wu, ¶[0016]),
a third input node (Third input node VB: Wu, Figure 1),
a fourth input node (Fourth input node VA: Wu, Figure 1),
a first output node and a second output node (Disclosing first and second output nodes: Wu, ¶[0017])
Wu discloses this configuration improves sensing and speed margins, particularly when detecting data line voltage differences that are small relative to intrinsic sense amplifier offset voltages (Wu, ¶[0011]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the sensitive sense amplifier of Wu with the dual DFE architecture of Lin, with a reasonable expectation of success. Both inventions are well known in the field of decision feedback equalizers and the combination of known inventions with predictable results is obvious and not patentable.
Neither Lin nor Wu disclose integrating currents on parasitic capacitors. Bulzacchelli, however, discloses a Decision Feedback Equalizer (DFE) comprising:
wherein a first current based on a voltage at the third input node is integrated on a first parasitic capacitance (Integrating a first current through Q4 on CH for VOUT- based on the gate voltage at Q4: Bulzacchelli, Figure 8B; Disclosing hold capacitances CH may comprise an on-chip capacitor or inherent parasitic capacitance: Bulzacchelli, col.7:64-67), and
a second current based on a voltage at the fourth input node is integrated on a second parasitic capacitance (Integrating a second current through Q3 on CH for VOUT+ based on the gate voltage at Q3: Bulzacchelli, Figure 8B),
Bulzacchelli teaches this configuration, which integrates current on a capacitor, and expressly teaches the use of parasitic capacitance, eliminates settling time requirements for the circuit, making it feasible to increase the number of taps without a significant power penalty (Bulzacchelli, col.2:1-6). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the parasitic capacitance of Bulzacchelli with the stage circuit architecture of Chong, with a reasonable expectation of success. Both inventions are well known in the field of Differential Feedback Equalizers and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 15, Lin discloses the system of claim 14, wherein the first decision feedback equalizer sense amplifier circuit and the second decision feedback equalizer sense amplifier circuit
each include
a current amplifier circuit (A current amplification circuit: Lin, Figure 5 and Lin, ¶[0028]) and
a voltage circuit coupled to the current amplifier circuit (A voltage circuit coupled to the current amplifier circuit: Lin, Figure 5).
Regarding Claim 19, Wu discloses the system of claim 14, further comprising:
a non-volatile memory array
coupled to the first decision feedback equalizer sense amplifier circuit and the second decision feedback equalizer sense amplifier circuit (A memory array connected to the first stage: Wu, ¶[0018]),
wherein data read from the non-volatile memory array comprises the data input signal (Data input signals DL and DLB being memory circuit data lines: Wu, ¶[0018]).
Claim(s) 16-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0023730 A1 to Feng Lin (hereafter Lin) in view of US 2023/0267970 A1 to Jui-Jen Wu, et al. (hereafter Wu) and US 8,085,841 B2 to John F. Bulzacchelli, et al. (hereafter Bulzacchelli) and further in view of US 2016/0344576 A1 to Pier Andrea Francese (hereafter Francese).
Regarding Claim 16, Lin discloses the system of claim 14, but does not clearly disclose the further limitations of Claim 16. Francese, however, discloses a decision feedback equalizer as in Claim 14, wherein the first decision feedback equalizer sense amplifier circuit comprises a first circuit stage configured to
integrate a current based on the data input signal (Data input signal V: Francese, ¶[0052]),
a signal at the first output node of the second decision feedback equalizer sense amplifier circuit (Feedback signals D-1- and D-2 cross connected back to the second DFE: Francese, ¶[0052]) and
a signal at the second output node of the second decision feedback equalizer sense amplifier circuit (Feedback signals D-1- and D-2 cross connected back to the second DFE: Francese, ¶[0052]).
Francese discloses this structure achieves higher amplifier gain while power consumption is reduced (Francese, ¶[0069]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the cross-coupled DFEs of Francese with the dual DFE architecture of Lin, with a reasonable expectation of success. Both inventions are well known in the field of Decision Feedback Equalizers and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 17, Lin discloses the system of claim 14, but does not clearly disclose the further limitations of Claim 17. Francese, however, discloses a decision feedback equalizer as in Claim 14, wherein the second decision feedback equalizer sense amplifier circuit comprises a first circuit stage configured to
integrate a current based on the data input signal (Data input signal V: Francese, ¶[0052]),
a signal at the first output node of the first decision feedback equalizer sense amplifier circuit (Feedback signals D-3- and D-4 cross connected back to the first DFE: Francese, ¶[0052]), and
a signal at the second output node of the first decision feedback equalizer sense amplifier circuit (Feedback signals D-3- and D-4 cross connected back to the first DFE: Francese, ¶[0052]).
Francese discloses this structure achieves higher amplifier gain while power consumption is reduced (Francese, ¶[0069]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the cross-coupled DFEs of Francese with the dual DFE architecture of Lin, with a reasonable expectation of success. Both inventions are well known in the field of Decision Feedback Equalizers and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Independent Claim 20, Lin discloses a method comprising:
determining a distortion characteristic of a communication channel (Disclosing making a determination to reduce the inter-symbol interference in a circuit: Lin, ¶[0015]); and
selectively activating a feedback circuit in the first decision feedback equalizer sense amplifier circuit based on the determined distortion characteristic (Selectively activating the DFE depending on the circuit requirements: Lin, ¶[0036]; Such as the level of ISI in the circuit: Lin, ¶[0023]), wherein:
the first decision feedback equalizer sense amplifier circuit and the second decision feedback equalizer sense amplifier circuit are configured to operate with a double data rate clocking scheme (The circuits configured to operate with a double data rate clocking scheme: Lin, ¶[0096]).
Lin does not expressly disclose these circuits laying between a memory array and the DFE. Wu, however, discloses a circuit as in Claim 20, including:
determining a distortion characteristic of a communication channel disposed between
a non-volatile memory array (A memory array connected to the first stage: Wu, ¶[0018]) and
a memory controller interface that comprises a first decision feedback equalizer sense amplifier circuit (A first DFE amplifier circuit connected to the input data lines: Wu, Figure 5).
Wu discloses this configuration improves sensing and speed margins, particularly when detecting data line voltage differences that are small relative to intrinsic sense amplifier offset voltages (Wu, ¶[0011]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the sensitive sense amplifier of Wu with the dual DFE architecture of Lin, with a reasonable expectation of success. Both inventions are well known in the field of decision feedback equalizers and the combination of known inventions with predictable results is obvious and not patentable.
Lin does not expressly disclose cross-connecting DFE circuits. Francese, however, discloses a DFE circuit as in Claim 20 wherein:
the feedback circuit in the first decision feedback equalizer sense amplifier circuit is configured to integrate a current based on a feedback signal from a second decision feedback equalizer sense amplifier circuit (Feedback signals D-1- and D-2 cross connected back to the second DFE: Francese, ¶[0052]).
Francese discloses this structure achieves higher amplifier gain while power consumption is reduced (Francese, ¶[0069]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the cross-coupled DFEs of Francese with the dual DFE architecture of Lin, with a reasonable expectation of success. Both inventions are well known in the field of Decision Feedback Equalizers and the combination of known inventions with predictable results is obvious and not patentable.
Francese does not disclose the integration of the DFE signal should be configured to integrate the current on a first parasitic capacitance. Bulzacchelli, however, discloses a Decision Feedback Equalizer wherein the current is integrated on a parasitic capacitor (Integrating a first current through Q4 on CH for VOUT- based on the gate voltage at Q4: Bulzacchelli, Figure 8B; Disclosing hold capacitances CH may comprise an on-chip capacitor or inherent parasitic capacitance: Bulzacchelli, col.7:64-67). Bulzacchelli teaches this configuration, which integrates current on a capacitor, eliminates settling time requirements for the circuit, making it feasible to increase the number of taps without a significant power penalty (Bulzacchelli, col.2:1-6). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the parasitic capacitance of Bulzacchelli with the stage circuit architecture of Chong, with a reasonable expectation of success. Both inventions are well known in the field of Differential Feedback Equalizers and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0023730 A1 to Feng Lin (hereafter Lin) in view of US 2023/0267970 A1 to Jui-Jen Wu, et al. (hereafter Wu) and US 8,085,841 B2 to John F. Bulzacchelli, et al. (hereafter Bulzacchelli) and further in view of US 11,037,607 B2 to Raymond Chong, et al. (hereafter Chong).
Regarding Claim 18, Lin discloses the system of claim 14, but fails to disclose the further limitations of Claim 18. Chong, however, discloses a DFE circuit as in Claim 14, further comprising:
a first clock signal coupled to the first decision feedback equalizer sense amplifier circuit (First clock signal clk connected to the first DFE: Chong, col.8:24); and
a second clock signal coupled to the first decision feedback equalizer sense amplifier circuit (Second clock signal Clkb connected to the first DFE: Chong, col.8:24),
wherein the second clock signal is an inverted version of the first clock signal (Wherein Clkb is the inverse of Clk: Chong, col.8:24).
Chong teaches using complementary clock signals permits the circuit to be set and reset (Chong, col.8:24-34). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the predictable clock signal of Chong with the dual DFE architecture of Lin, with a reasonable expectation of success. Both inventions are well known in the field of DFE circuitry and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 8,704,583 B2 to John F. Bulzacchelli, et al.: Disclosing a cross-connected current interrogating amplifiers stabilized by capacitors.
US 2013/0002325 A1 to Minjae Lee: Disclosing cross-connected latches controlled by clock cycles.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 04/17/2026
Prosecution Insights