Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 9, 10, 17, 18, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 9, the prior art fails to teach in combination with the rest of the limitations in the claim: “a third buffer coupled to the DUT interface node using the first sense
resistor, the second sense resistor, and a third sense resistor; and
a third range switch configured to selectively couple the third sense
resistor to receive the auxiliary control signal.”
With respect to claim 17, the prior art fails to teach in combination with the rest of the limitations in the claim: “determining the resistance of the first
sense resistor includes:
providing the first current signal to the first sense resistor using a first
range switch;
measuring a first voltage across the first sense resistor using second and
third switches; and
determining the resistance of the first sense resistor based on a
magnitude of the first current signal and the measured first voltage;
wherein the second and third switches comprise a portion of a first
semiconductor die of a first semiconductor type, and wherein the first range
switch comprises a portion of a second semiconductor die of a second
semiconductor type.”
Claim 10 is objected to due to its dependency on claim 9; claim 18 is allowable due to their dependency on claim 16; claim 19 is allowable due to its dependency on claim on 18; claim 20 is allowable due to its dependency on claim 19;
Allowable Subject Matter
Claims 11-15 are allowed.
With respect to claim 11, the prior art fails to teach in combination with the rest of the limitations in the claim: “a second IC comprising a portion of a second semiconductor die of a
second semiconductor type, the second IC comprising: the output buffer circuit;
a first sense resistor coupled to a first buffer and the DUT node; and
a first range switch coupled to the first sense resistor and an auxiliary
driver input node, wherein the auxiliary driver input node is configured to
receive an auxiliary drive signal from the external auxiliary controller.”
Claims 12, 13 and 15 are allowable due to their dependencies on claim 11; claim 14 is allowable due to its dependency on claim 13;
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 16, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over McQuilkin et al. (U.S. Patent No. 11,686,773 B1) in view of Kernahan (U.S. Patent No. 6,891,355 B2).
With respect to claim 1, McQuilkin et al. discloses a test equipment system for providing signals to, or receiving signals from, a device under test (DUT) (see DUT block 124 shown in Fig. 1), the system comprising:
output buffer circuitry (see Drivers A and Driver AB blocks which are shown in Fig. 1) configured to provide a DUT signal to the DUT at a DUT interface node in response to a force control signal at a buffer control node (these drivers are pattern/logic drivers shown in Fig. 1);
a first sense resistor coupled to the DUT interface node [124] (shown in Fig. 1) and the output
buffer circuitry (see resistor element 106 shown in Fig. 1);
a first range switch coupled to the first sense resistor and an auxiliary
driver input node (a relatively large current switch stage that can be coupled directly to the DUT signal 130. A current switching stage in the first DriverA 104 can alternately switch current into and out of the DUT signal 130 in response to a control signal Swing 118, such as can be a voltage control signal);
controller circuitry configured to provide the force control signal at the
buffer control node (the systems can include control circuits to precisely control switching control voltage signals and switching current signals, and to control an operating mode and monitoring or measuring activity of a comparator; col. 3, lines 39-42).
McQuilkin et al. does not disclose an auxiliary control circuit configured to bypass the controller circuitry and selectively provide an auxiliary control signal at one of the buffer control
node and the auxiliary driver input node.
Kernahan discloses an auxiliary control circuit configured to bypass the controller circuitry and selectively provide an auxiliary control signal at one of the buffer control
node and the auxiliary driver input node (col. 38, lines 45-63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of McQuilkin et al. to include an auxiliary control circuit configured to bypass the controller circuitry and selectively provide an auxiliary control signal at one of the buffer control node and the auxiliary driver input node as taught by Kernahan to predictably improve overall system performance and reliability.
With respect to claim 2, the combination of McQuilkin et al. and Kernahan discloses the test equipment system of claim 1, wherein the auxiliary control circuit is configured to provide the auxiliary control signal as a current signal at the auxiliary driver input node (see Kernahan col. 38, lines 45-63).
With respect to claim 3, the combination of McQuilkin et al. and Kernahan discloses the test equipment system of claim 2, comprising voltage sense circuitry configured to measure a voltage signal across the first sense resistor in response to the current signal (see McQuilkin et al. resistor 106 shown in Fig. 1).
With respect to claim 4, the combination of McQuilkin et al. and Kernahan discloses the test equipment system of claim 1, wherein the auxiliary control circuit is configured to provide the auxiliary control signal as a voltage signal at the buffer control node (see McQuilkin et al. a relatively large current switch stage that can be coupled directly to the DUT signal 130. A current switching stage in the first DriverA 104 can alternately switch current into and out of the DUT signal 130 in response to a control signal Swing 118, such as can be a voltage control signal).
With respect to claim 5, the combination of McQuilkin et al. and Kernahan discloses the test equipment system of claim 1, comprising a bypass circuit configured to selectively couple the buffer control node to the controller circuitry or to the auxiliary control circuit (see Kernahan col. 38, lines 45-63).
With respect to claim 6, the combination of McQuilkin et al. and Kernahan discloses the test equipment system of claim 1, wherein the output buffer circuitry
comprises multiple buffers coupled to the DUT using respective sense resistors (see McQuilkin et al. resistor 106 shown in Fig. 1),
and wherein one or more of the multiple buffers (see McQuilkin et al. buffers 102 and 104, which are drivers A and AB shown in Fig. 1) is selected to provide the DUT (see McQuilkin et al. DUT 124 shown in Fig. 1) signal to the DUT interface node based on a characteristic of the force control
signal at the buffer control node (the systems can include control circuits to precisely control switching control voltage signals and switching current signals, and to control an operating mode and monitoring or measuring activity of a comparator; col. 3, lines 39-42).
With respect to claim 7, the combination of McQuilkin et al. and Kernahan discloses the test equipment system of claim 6, wherein the multiple buffers comprise:
a first buffer (see McQuilkin et al. showing a first buffer 102 driver A shown in Fig. 1) coupled to the DUT interface node using the first sense
resistor (see McQuilkin et al. 124 showing DUT and first sense resistor 106 shown in Fig. 1); and a second buffer coupled to the DUT interface node using the first sense
resistor and a second sense resistor (see McQuilkin et al. second buffer driver A show in Fig. 1 connected to the resistor 106 shown in Fig. 1).
With respect to claim 8, the combination of McQuilkin et al. and Kernahan discloses the test equipment system of claim 7, comprising a second range switch
configured to selectively couple a second driver input node to the second sense
resistor (see McQuilkin et al. a relatively large current switch stage that can be coupled directly to the DUT signal 130. A current switching stage in the first DriverA 104 can alternately switch current into and out of the DUT signal 130 in response to a control signal Swing 118, such as can be a voltage control signal).
With respect to claim 16, McQuilkin et al. discloses a method for calibrating an automated test equipment (ATE) system, the
method comprising:
determining a resistance of a first sense resistor (see resistor element 106 shown in Fig. 1), wherein the first sense resistor is coupled to a device under test (DUT) node of the system (see DUT 124 shown in Fig. 1); using one or more buffers in an output stage of the system to provide
an output current at the DUT node via the first sense resistor (see Drivers A and Driver AB blocks which are shown in Fig. 1);
measuring the output current at the DUT node (measuring an output signal 128 shown in Fig. 1; col. 7, lines 1-13); and providing offset information about the one or more buffers in the output
stage based on the measured output current (see Drivers A and Drivers AB which are considered buffers in Fig. 1).
McQuilkin et al. does not disclose using a first current signal from an external auxiliary controller.
Kernahan discloses using a first current signal from an external auxiliary controller.
(col. 38, lines 45-63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of McQuilkin et al. to include an auxiliary control circuit configured to bypass the controller circuitry and selectively provide an auxiliary control signal at one of the buffer control node and the auxiliary driver input node as taught by Kernahan to predictably improve overall system performance and reliability.
With respect to claim 21, McQuilkin et al. discloses a method for calibrating an automated test equipment (ATE) system, the
method comprising:
determining a resistance of a first sense resistor (see resistor element 106 shown in Fig. 1, wherein the first sense resistor is coupled to a device under test (DUT) node of the system (see resistor element 106 coupled to DUT 124 shown in Fig. 1);
generating a first force control signal using a local controller for a
parametric measurement unit of the system (col. 6, lines 47-54);
receiving the force control signal at output buffer circuitry and, in
response, providing a first DUT signal to a DUT at the DUT node (see DUT 124 and signal from the DUT 130 into a digital representation from the output signal 128 shown in Fig. 1), and
measuring a voltage across the first sense resistor (see resistor element 106 shown in Fig. 1; col. 5, lines 13-25);
determining a current at the DUT node based on the measured voltage
and the determined resistance of the first sense resistor (see sense resistor 106 shown in Fig. 1); and
updating a characteristic of the local controller based on the determined
current at the DUT node (see resistor col. 5, lines 6-11).
McQuilkin et al. does not disclose using a first current signal from an external auxiliary controller.
Kernahan discloses using a first current signal from an external auxiliary controller.
(col. 38, lines 45-63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of McQuilkin et al. to include an auxiliary control circuit configured to bypass the controller circuitry and selectively provide an auxiliary control signal at one of the buffer control node and the auxiliary driver input node as taught by Kernahan to predictably improve overall system performance and reliability.
With respect to claim 22, McQuilkin et al. discloses the method of claim 21, wherein updating the characteristic of the local controller includes updating an offset for a digital-to-analog converter (DAC) circuit that is configured to control operation of the local controller (col. 7, lines 1-13).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARHANA AKHTER HOQUE whose telephone number is (571)270-7543. The examiner can normally be reached Monday-Friday, 7:30am-4:00pm.
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/FARHANA A HOQUE/Primary Examiner, Art Unit 2858