DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see remarks, filed 08-14-25, with respect to the rejection(s) of claim(s) 1,2,7-9, 15 and 17 under 35 USC 103 have been fully considered and are persuasive(re claims 15 and 17). A new ground(s) of rejection is made in view of new cite to Matsue and Ho(of record).
Claim Objections
Claim 13 objected to because of the following informalities: Please delete the “(d)” notation for the last para in the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 7-9, 15, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho(US 6,809,603, of record) in view of Matsue(US 7,180,794)new cite.
Re claim 1, 3 and 15 and 17:
The main reference, Ho ‘603, shows an oscillator(30, ring type), with a voltage supply variation reduction circuit (including Bias circuit 32) configured to be coupled to a voltage source(Vdd in module 32) and to pass a first current (I0 )as a function of the voltage source(Vdd) exceeding a selected value (Vdiode(50));
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a bias generation circuit(32), coupled to the voltage supply variation reduction circuit and configured to be coupled to the voltage source(Vdd), the bias generation circuit configured to pass a second current (I1)when the voltage of the voltage source exceeds the selected value(V Vdiode), wherein the second current is essentially constant at stable temps;
a temperature-compensation circuit including( 44b )and (resistance 54), configured to be coupled to the voltage source(Vdd), the temperature-compensation circuit configured to pass a temperature-compensated third current(I2) through the at least one FET(46); and oscillator circuitry(ring osc) coupled to the temperature-compensation circuit and configured to pass the temperature-compensated current and generate an output comprising a periodic waveform (F0).
The main reference, Ho, does not show the NMOSFET (46)and a negative temperature coefficient resistor while the NFET has a positive temp coefficient with capacitive loading. Threshold temp characteristic(s) is not described.
Lastly, gating (claim 16)a ring oscillator, that is, using a NAND type gate with enable signal is not shown.
The reference to Matsue shows use of negative resistances with the MOSFET inverters(PMOS,NMOS)and conventionally these MOSFET's on-resistance have a positive temperature coefficient; meaning, it increases with temperature; the reference to Matsue, see conventional figures 8 and 9, below, showing the n-stage ring osc(>=5 stages), for example, where the resistors R11,Rnn are negative temp coefficient types, with the NMOSFET in series. Figure 9 showing capacitors coupled to the output node and reference potential(GND) for each stage.
The examiner takes official notice with regards the conventional MOSFET's on-resistance has a positive temperature coefficient, increasing with temperature, generally, while at a threshold voltage, it has a negative temperature coefficient, decreasing as temperature rises(clm 3).
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The reference shows more than the five stages, however, for a certain number(5 stages) this is a simple matter of design consideration, depending on frequency where the negative temp resistors are placed on all stages to enhance the frequency stability(clm 17).
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Finally, gating a ring oscillator, that is, using a NAND type gate(claim 16) to allow for an enable signal to trigger the ring, is conventional and examiner will take official notice with regards this function(see cited reference below).
In light of the above it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have recognized that temperature compensated ring oscillator shown by Ho may include several conventional enhancing features such as the negative temp coeff resistors and capacitive loading, shown by Matsue, as a simple matter of design consideration, and thus benefit from further temperature compensation. The particular number of RO stages being another simple matter of design consideration for frequency. Enabling the RO operation with use of a NAND gate is also conventional. Ultimately, the idea is to keep the oscillator clock frequency constant in view of the known temp and bias changes.
Re claims 7, 8 and 9: the oscillator clock frequency remains constant in light of ambient temp variations that also affect the voltage source/biasing.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The reference to Chen shows the use of NAND gate with enable signal inputs for the ring oscillators, see abstract figure.
Allowable Subject Matter
Claims 13 and 14 are allowed.
Claims 5, 6 and 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ARNOLD M. KINKEAD
Primary Examiner
Art Unit 2849
/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2849