Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species III, Fig. 4, in the reply filed on June 26, 2026, is acknowledged.
Claims 7, 9, 11, are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 26, 2026.
Regarding claim 19, the elected species does not teach “wherein the third width (of the second gate bus segment) is greater than the fourth width.” If the second portion 112B in Fig. 4 is taken to be the first gate bus segment recited in claim 1, then the first portion 112A would need to be taken as the second gate bus segment. However, the first portion 112A has a constant width, and would thus fail to read on the cited limitation in claim 19. On the other hand, if the first portion 112A is taken to be the first gate bus segment recited in claim 1, then it would fail to read on the limitation, “wherein the first width (of the first gate bus segment) is greater than the second width”, recited therein.
Specification
The abstract of the disclosure is objected to because:
In line 1, “includes semiconductor layer” should be “includes a semiconductor layer”.
In line 4, “adjacent the first end” should be “adjacent to the first end”.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
In paragraph [0006], “includes semiconductor layer” should be “includes a semiconductor layer”.
In paragraph [0007], “adjacent the first end” should be “adjacent to the first end”.
Appropriate correction is required.
Claim Objections
Claims 1 and 4 are objected to because of the following informalities:
In claim 1, line 2, “semiconductor layer” should be “a semiconductor layer”.
In claim 1, line 7, “adjacent the first end” should be “adjacent to the first end”.
In claim 4, line 3, “gate pad wherein longitudinal gate fingers” should be “gate pad, and wherein longitudinal gate fingers”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 4-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation, “a gate pad on the semiconductor layer”. Claim 1, which this claim is dependent on, already recites “a gate pad on the semiconductor layer”, so it is unclear whether the gate pad recited in this claim is the same gate pad as recited in claim 1 or a different gate pad.
Claim 4 recites the limitation, “a gate pad on the semiconductor layer”. Claim 1, which this claim is dependent on, already recites “a gate pad on the semiconductor layer”, so it is unclear whether the gate pad recited in this claim is the same gate pad as recited in claim 1 or a different gate pad.
Claim 5 recites the limitation, “wherein the first gate bus segment supplies a gate current to the gate finger.” It is unclear how the first gate bus segment is able to supply a current to the gate finger, as no electrical connection between the two elements is recited either in this claim or in its parent claim, claim 1.
The following will be assumed for examination purposes:
The gate pads recited in claims 2 and 4 are the same gate pad recited in claim 1.
There is an electrical connection between the first gate bus segment and the gate finger.
These rejections may be overcome by:
Either reciting a second gate pad in each of claims 2 and 4 or amending the claims to remove the (redundant) recitation of “a gate pad”.
Amending claim 5 to recite an electrical connection between the first gate bus segment and the gate finger. This would also overcome the rejection under 35 U.S.C. 112(d) detailed below.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 5 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 5 recites the limitation, “wherein the first gate bus segment supplies a gate current to the gate finger.” This limitation confers no structural difference on the apparatus, merely reciting a function of the first gate bus segment, and thus carries no patentable weight. Since it is the only new limitation recited in the claim, the claim fails to further limit the scope of its parent claim, claim 1.
For examination purposes, the new limitation recited in claim 5 will be interpreted as a recitation of an electrical connection between the first gate bus segment and the gate finger.
Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
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Fig. 14 of Zuo, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 10, and 12-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zuo et. al., Pub. No. US 2024/0194599, hereafter referred to as Zuo.
Regarding claim 1, Zuo teaches all of the limitations of the claim in Fig. 14, reproduced above with annotations added by the examiner: “A semiconductor device comprising: semiconductor layer” ([0063]: “Further, the semiconductor device further includes a substrate. The cells, the gate pad, the emitter pad, the collector pad, the gate busbar and the gate lines of the semiconductor device are all formed on the substrate. The material of the substrate may be silicon, silicon carbide, gallium nitride or the like, which are not restricted in the present disclosure.”); “a gate pad on the semiconductor layer” ([0105]; Fig. 14, gate pad 11); “a longitudinal gate finger on the semiconductor layer, the longitudinal gate finger having opposing first and second ends” ([0105]; Fig. 14, trench gates 13; note that each trench gate 13 has two opposing ends); “and a first gate bus segment on the semiconductor layer” ([0105]; Fig. 14, first portions 121 of the gate busbars 12), “wherein the first gate bus segment extends adjacent the first end of the longitudinal gate finger” (Fig. 14; note that the first portions 121 are adjacent to the opposing ends of trench gates 13); “wherein the first gate bus segment has a proximal end nearest the gate pad” (Fig. 14; note that the first portions 121 have an end on the same side of the device along the Y axis as the gate pad 11) “and a distal end farthest from the gate pad” (Fig. 14; note that the first portions 121 have an end on the opposite side of the device along the Y axis as the gate pad 11); “wherein the first gate bus segment has a first width at the proximal end and a second width at the distal end” (Fig. 14, first and second widths); “wherein the first width is greater than the second width” ([0105]; Fig. 14, note that the first width is greater than the second width).
Regarding claim 2, Zuo further teaches “The semiconductor device of Claim 1, further comprising a gate pad on the semiconductor layer” ([0105]; Fig. 14, gate pad 11), “wherein the first gate bus segment is in electrically conductive contact with the gate pad” ([0105]: “The second portion 122 connects the plurality of first portions 121 to the gate pad 11.”; Fig. 14; note that the gate busbar 12, which includes the first portions 121, is in direct contact with the gate pad 11).
Regarding claim 3, Zuo further teaches “The semiconductor device of Claim 1, further comprising a plurality of longitudinal gate fingers on the semiconductor layer” ([0105]: “As shown in FIG. 14, the semiconductor device includes… a plurality of trench gates 13.”), “wherein the plurality of longitudinal gate fingers have different lengths” (Fig. 14; note that the trench gates 13 depicted have different lengths).
Regarding claim 4, Zuo further teaches “The semiconductor device of Claim 3, further comprising a gate pad on the semiconductor layer” ([0105]; Fig. 14, gate pad 11), “wherein the first gate bus segment is in electrically conductive contact with the gate pad” ([0105]; Fig. 14; note that the gate busbar 12, which includes the first portions 121, is in direct contact with the gate pad 11) “wherein longitudinal gate fingers farther from the gate pad have larger lengths than longitudinal gate fingers closer to the gate pad” (Fig. 14; note that the trench gates 13 closer to the gate pad 11 are shorter in length than those further away).
Regarding claim 5, Zuo further teaches “The semiconductor device of Claim 1, wherein the first gate bus segment supplies a gate current to the gate finger” ([0105]: “The gate busbar 12 includes a plurality of first portions 121 each disposed along a second axis A2. The plurality of first portions 121 are connected to the plurality of trench gates 13.”; Fig. 14, gate busbar 12, first portions 121, trench gates 13; note that the connection between the first portions 121 and the trench gates 13 enable the first portions 121 to supply current to the trench gates 13).
Regarding claim 10, Zuo further teaches “The semiconductor device of Claim 1, wherein the first gate bus segment increases in width monotonically from the distal end to the proximal end thereof” (Fig. 14; note that the widths of the first sub-portions 1211 of the first portions 121 only become wider as they get closer to the gate pad 11, with no intervening sub-portions being narrower).
Regarding claim 12, Zuo further teaches “The semiconductor device of Claim 1, further comprising a second gate bus segment” ([0105]; Fig. 14, second portions 122) “that conductively connects the proximal end of the first gate bus segment to the gate pad” ([0105]: “The second portion 122 connects the plurality of first portions 121 to the gate pad 11.”; also see Fig. 14).
Regarding claim 13, Zuo further teaches “The semiconductor device of Claim 12, wherein the second gate bus segment has a uniform width” (Fig. 14; note that the second portions 122 have uniform widths over their entire lengths; also see [0024]: “In an embodiment of the present disclosure, widths or thicknesses of the plurality of first sub-portions change in a second direction, the second direction parallels to the second axis and points toward a side away from the gate pad” (Fig. 14, Y axis, direction A2), “and lengths of the plurality of first sub-portions change in the second direction” (Fig. 14, first sub-portions 1211), “and the second portion has a uniform width along the first axis.” (Fig. 14, second sub-portions 122, direction A1)).
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Fig. 4 of Yao, reproduced with annotations added by the examiner.
Claims 1, 6, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yao et. al., Pub. No. CN 114220853A, hereafter referred to as Yao.
Regarding claim 1, Yao teaches all of the limitations of the claim in Fig. 4, reproduced above with annotations added by the examiner: “A semiconductor device comprising: semiconductor layer” ([0043]; Fig. 4, active region 10; see also [0063]: “The following description focuses on the key differences. For other structural details, please refer to the relevant records mentioned above. They will not be repeated here.”); “a gate pad on the semiconductor layer” ([0043]; Fig. 4, gate pad 12; note that the gate pad is mislabeled as 11 in the figure; see also [0043]: “…an on-chip gate resistor 14 is connected to the ring-shaped gate bus 13 and the gate pad 12 respectively.” and [0063]); “a longitudinal gate finger on the semiconductor layer, the longitudinal gate finger having opposing first and second ends” ([0052]: “…the trench A is arranged vertically from bottom to top…”; Fig. 4, trenches A; note that each trench A has two opposing ends; also see [0063]); “and a first gate bus segment on the semiconductor layer” ([0042]; Fig. 4, first portions of the gate bus 13; also see [0063]), “wherein the first gate bus segment extends adjacent the first end of the longitudinal gate finger” (Fig. 4; note that the first portions of the gate bus 13 are adjacent to one end of each of the trenches A); “wherein the first gate bus segment has a proximal end nearest the gate pad” (Fig. 4; note that the first portions of the gate bus 13 have an end close to the gate pad 12) “and a distal end farthest from the gate pad” (Fig. 4; note that the first portions of the gate bus 13 have an end farthest from the gate pad 12); “wherein the first gate bus segment has a first width at the proximal end and a second width at the distal end” (Fig. 4, first and second widths); “wherein the first width is greater than the second width” ([0064]: “Specifically, the gate bus corresponding to the first side is convex in shape, and the width of the two edges of the gate bus gradually decreases linearly as it extends from the junction with the middle part of the first side toward the second side.”).
Regarding claim 6, Yao further teaches “The semiconductor device of Claim 1, wherein the first gate bus segment increases in width uniformly from the distal end to the proximal end thereof” ([0064]; note that a linear increase towards the middle of the first side is necessarily a uniform increase).
Regarding claim 8, Yao further teaches “The semiconductor device of Claim 1, wherein the first gate bus segment increases in width linearly from the distal end to the proximal end thereof” ([0064]).
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Fig. 1C of Lichtenwalner, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Zuo in view of Lichtenwalner et. al., Pub. No. US 2022/0149165, hereafter referred to as Lichtenwalner.
Regarding claim 22, Zuo teaches “The semiconductor device of Claim 1”, but does not teach “further comprising a silicide region in the semiconductor layer, wherein the gate pad, the first gate bus segment and the longitudinal gate finger are provided within a periphery of the silicide region.” However, Zuo does teach that the gate busbars may be made of AlSiCu, which is a metal silicide (Zuo [0061]: “In the embodiments of the present disclosure, the material of the gate busbar may include metals and/or alloys such as… AlSiCu.”).
Lichtenwalner, on the other hand, teaches a similar device (Lichtenwalner Figs. 1C) in which the gate pad, gate fingers, and gate buses are formed as one continuous piece (Lichtenwalner [0090]: “It will be appreciated that the gate finger 134 may be part of the continuous gate electrode layer 130 (see FIGS. 1C and 1D) that includes the gate pad 132, the plurality of gate fingers 134, and the one or more gate buses 136.”). Furthermore, Lichtenwalner teaches embodiments of their invention that use metal silicides as the materials of one or both of the gate fingers and gate buses (Lichtenwalner [0011]: “In some embodiments, the gate finger comprises a first material and the gate bus comprises a second material that is different from the first material.”, [0012]: “In some embodiments, the second material of the gate bus comprises a layer of silicide…”, [0043]: “In some embodiments, the first material comprises… silicide.”).
The teaching of a gate pad, gate fingers, and gate buses formed as one continuous piece of Lichtenwalner along with the teaching of metal silicides as possible materials for the gate fingers and gate buses can be incorporated into the device of Zuo by making the gate pad, trench gates, and gate busbars out of a metal silicide. The combined device teaches “further comprising a silicide region in the semiconductor layer” (Zuo [0105]; Fig. 14, gate pad 11, gate busbars 12, trench gates 13; Lichtenwalner [0011-0012] and [0043]; note that these are all made of a metal silicide in the combined device), “wherein the gate pad, the first gate bus segment and the longitudinal gate finger are provided within a periphery of the silicide region” (Zuo Fig. 14; note that the gate pad 11, gate busbars 12, and the topmost trench gate 13 are on the periphery of the overall silicide region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to make the gate pad, gate busbars, and trench gates of Zuo out of a metal silicide as taught by Lichtenwalner because metal silicides are known to be conductors and thus suitable materials for these elements and it would be a simple substitution of one material for another.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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