DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-6 and 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty in the different boundaries and new claim limitations “(i) a first part of the back side interconnect and the underfill and (ii) a second part of the back side interconnect and the side surface of the first integrated device.” The claim is indefinite because it is not clear where a first part and a second part of the back side interconnect starts and ends. The claim is also unclear if the first part is also a first part of the underfill.
Regarding claim 4, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty in the different boundaries and new claim limitations “a third part of the back side interconnect and the back side of the first integrated device.” The claim is indefinite because it is not clear where a third part of the back side interconnect and the back side of the first integrated device starts and ends.
Regarding claim 5, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty in the different boundaries and new claim limitations “a fourth part of the back side interconnect and another part of the underfill that is coupled to and touching another surface of the first integrated device..” The claim is indefinite because it is not clear where a fourth part of the back side interconnect and the another part of the underfill starts and ends.
Regarding claim 6, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty in the different boundaries and new claim limitations “a fourth part of the back side interconnect and another side surface of the first integrated device.” The claim is indefinite because it is not clear where a fourth part of the back side interconnect and the another side surface of the first integrated device starts and ends.
Regarding claim 13, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty in the different boundaries and new claim limitations “a first part of the back side interconnect and a back side of the first integrated device, and wherein a second part of the back side dielectric layer is located between a second part of the back side interconnect.” The claim is indefinite because it is not clear where a first part of the back side interconnect and a second part of the back side dielectric layer starts and ends.
Regarding claim 14, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty in the different boundaries and new claim limitations “wherein a first part of the back side dielectric layer is located between a first part of the back side interconnect and the back side of the first integrated device, wherein a second part of the back side dielectric layer is located between a second part of the back side interconnect and the back side of the second integrated device, and wherein a third part of the back side dielectric layer is located between a third part of the back side interconnect and a surface of the underfill.” The claim is indefinite because it is not clear where the first, second and third part of the back side dielectric layer starts and ends.
Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention.
For purposes of evaluating the prior art, the examiner interprets the parts as any point or section on the surface of the elements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 18, 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tomita et al. US 2007/0231953.
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Regarding claim 1, Tomita et al. Fig. 3A and [0018]-[0038] disclose a package comprising: a substrate 210 [0031]-[0032];
a first integrated device 220 [0032]-[0035] coupled to the substrate 210 through at least a first plurality of solder interconnects 225 [0032];
an underfill 230 [0031]-[0032] located between the first integrated device 220 and the substrate 210; and
a back side interconnect 320 [0036] located over the underfill 230 and a back side of the first integrated device 220, and wherein the back side interconnect comprises metal [0036] that is coupled to and touching (i) a surface of the underfill 230 and (ii) a side surface of the first integrated device 220.
Regarding claim 2, Tomita et al. Fig. 3A and [0018]-[0038] disclose the package of claim 1, wherein the back side interconnect 320 is further coupled to and touching a back side surface of the first integrated device 220.
Regarding claim 18, Tomita et al. Fig. 3A and [0018]-[0038] disclose the package of claim 1, wherein the back side interconnect 320 includes copper (Cu) or silver (Ag) [0036].
Regarding claim 19, Tomita et al. Fig. 3A and [0018]-[0038] disclose the package of claim 1, wherein the back side interconnect includes an inkjet printed interconnect [0036].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-5 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomita et al. US 2007/0231953.
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Regarding claim 3, Tomita et al. Fig. 3A and [0018]-[0038] disclose a package comprising: a substrate 210 [0031]-[0032];
a first integrated device 220 [0032]-[0035] coupled to the substrate 210 through at least a first plurality of solder interconnects 225 [0032];
an underfill 230 [0031]-[0032] located between the first integrated device 220 and the substrate 210; and
a back side interconnect 320 [0036] located over the underfill 230 and a back side of the first integrated device 220, wherein the back side interconnect comprises metal [0036
Tomita et al. Fig. 3A and [0018]-[0038] do not expressly disclose a back side dielectric layer coupled to and touching (i) the underfill, (ii) a side surface of the first integrated device and (iii) a back side surface of the first integrated device, wherein the back side dielectric layer touching (i) the underfill, (ii) a side surface of the first integrated device and (iii) a back side surface of the first integrated device is part of the same continuous dielectric layer; metal that is coupled to and touching the back side dielectric layer, wherein the back side dielectric layer is located between (i) a first part of the back side interconnect and the underfill and (ii) a second part of the back side interconnect and the side surface of the first integrated device.
However, Tomita et al. in [0004] teach that metal interconnects are used to connect various elements in a semiconductor die. The interconnects provide electrically conducting paths to carry currents or provide power for various devices or circuits. Within an integrated circuit die, metal layers are stacked on top of one another by using dielectrics that insulate the metal layers from each other.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate a dielectric layer as taught by Tomita to couple to and touch (i) the underfill 230, (ii) a side surface of the first integrated device 220 and (iii) a back side surface of the first integrated device 220, wherein the back side dielectric layer touching (i) the underfill 230, (ii) a side surface of the first integrated device 220 and (iii) a back side surface of the first integrated device 220 is part of the same continuous dielectric layer; the metal layer coupled to and touching the back side dielectric layer, wherein the back side dielectric layer is located between (i) a first part of the back side interconnect 320 and the underfill 230 and (ii) a second part of the back side interconnect 320 and the side surface of the first integrated device 220 to insulate the metal layer of the back side interconnect.
Regarding claim 4, Tomita et al. Fig. 3A and [0018]-[0038] teach the package of claim 3, wherein the back side dielectric layer is located between a third part of the back side interconnect 320 and the back side of the first integrated device 220 (annotated above, e.g. in relation to the back side interconnect).
Regarding claim 5, Tomita et al. Fig. 3A and [0018]-[0038] teach the package of claim 4, wherein a part of the back side dielectric layer is located between a fourth part of the back side interconnect 320 and another part of the underfill 230 that is coupled to and touching another surface of the first integrated device 220 (annotated above, e.g. in relation to the back side interconnect).
Regarding claim 20, Tomita et al. Fig. 3A and [0018]-[0038] disclose the package of claim the package of claim 1, but do not expressly disclose wherein the back side interconnect includes plated interconnects.
Although Tomita et al. do not disclose the back side interconnect includes plated interconnects as that claimed by the Applicant, the material differences are considered obvious design choices and are not patentable unless obvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious before the effective filing date of the invention. See MPEP 2144.07
Allowable Subject Matter
Claims 6, 7 and 8-13 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art neither anticipates nor renders obvious, in the context of the claims,
Regarding claim 6, wherein a part of the back side dielectric layer is located between a fourth part of the back side interconnect and another side surface of the first integrated device.
Although various prior art references disclose several individual limitations in the claims, these references, and their combinations, neither anticipate nor render obvious the above identified limitation(s), as structured and interrelated in the context of the claims.
For example, Kim et al. US 2016/0247767. Tomita et al. Fig. 3A and [0018]-[0038] teach the package of claim 4 but does not expressly disclose, wherein a part of the back side dielectric layer is located between a fourth part of the back side interconnect 320 and another side surface of the first integrated device 220.
Kim et al. in Fig. 2I teach a semiconductor package including a dielectric layer 400 [0054]-[0056] is a continuous layer over and around the semiconductor components but fail to disclose the above noted limitations, in the context of the claims.
Regarding claim 7, wherein the back side interconnect is coupled to a first interconnect and a second interconnect from the plurality of interconnects of the substrate.
Although various prior art references disclose several individual limitations in the claims, these references, and their combinations, neither anticipate nor render obvious the above identified limitation(s), as structured and interrelated in the context of the claims.
For example, Kim et al. US 2016/0247767. Tomita et al. Fig. 3A and [0018]-[0038] disclose the package of claim 1, but do not expressly disclose wherein the substrate comprises:
at least one dielectric layer; and a plurality of interconnects, and wherein the back side interconnect is coupled to a first interconnect and a second interconnect from the plurality of interconnects of the substrate.
Kim et al. in Figs. 2A-2C teach a semiconductor package including an interposer substrate 100 [0029] having at least one dielectric layer 111 [0029]; and a plurality of interconnects 120 [0030] but do not expressly teach the above noted limitation.
Regarding claim 8, further comprising a second integrated device coupled to the substrate through at least a second plurality of solder interconnects, wherein the underfill is located between the second integrated device and the substrate. Claims 9-13 and 15-17 depend from claim 8.
Although various prior art references disclose several individual limitations in the claims, these references, and their combinations, neither anticipate nor render obvious the above identified limitation(s), as structured and interrelated in the context of the claims.
For example, Kelly et al. US 2017/0133310 fail to disclose the above noted limitations, in the context of the claims.
Claim 14 is allowed over the prior art. The following is a statement of reasons for the indication of allowable subject matter:
the prior art neither anticipates nor renders obvious, in the context of the claims, a back side dielectric layer coupled to the underfill, a back side of the first integrated device and a back side of the second integrated device;
a back side interconnect located over (i) the underfill, (ii) the back side of the first integrated device and (iii) the back side of the second integrated device; wherein a first part of the back side dielectric layer is located between a first part of the back side interconnect and the back side of the first integrated device,
wherein a second part of the back side dielectric layer is located between a second part of the back side interconnect and the back side of the second integrated device, and
wherein a third part of the back side dielectric layer is located between a third part of the back side interconnect and a surface of the underfill.
Although various prior art references disclose several individual limitations in the claims, these references, and their combinations, neither anticipate nor render obvious the above identified limitation(s), as structured and interrelated in the context of the claims.
For example, Kelly et al. US 2017/0133310 fail to disclose the above noted limitations, in the context of the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Sonya McCall-Shepard/ Primary Examiner, Art Unit 2898
