DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application. Claims 11-20 are withdrawn from further consideration.
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1: claims 1-10 in the reply filed on 12 August 2026 is acknowledged.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 15 May 2024. The information therein was considered.
Claim Objections
Claim 5 and 10 are objected to because of the following informalities:
In claim 5, p.2 line 2-3 “the interconnect” should be replaced with the first interconnect--.
The following amendment is suggested for claim 10:
10 (amended). The semiconductor device of claim 1, wherein the memory die further comprises: a plurality of sub-dies, stacked on each other along a stacking direction of the first tier and the second tier, each comprising: a second substrate having a third side and a fourth side opposite to the third side, the third side being closer to the active side of the memory die than the fourth side is; a third interconnect, disposed over the third side of the second substrate; a plurality of second through vias, embedded in the second substrate and electrically coupled to the third interconnect; and the plurality of second connecting structures, disposed over the third side of the second substrate and electrically coupled to the plurality of second through vias, a third pitch being between two adjacent second connecting structures of the plurality of second connecting structures, wherein the third interconnect is disposed between the plurality of second connecting structures and the second substrate, wherein the third pitch corresponds to a pitch being between two adjacent first connecting structures of the plurality of first connecting structures.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2021/0066254) (hereinafter, “Yu”).
Re: independent claim 1, Yu discloses in fig. 1 a semiconductor device, comprising: a first tier, comprising a semiconductor die (102), the semiconductor die comprising a plurality of first connecting structures (108 in fig. 4C) distributed over a non-active side of the semiconductor die; and a second tier, disposed over the first tier and comprising a memory die (110, 120), the memory die comprising a plurality of second connecting structures (118, 128 in fig. 4C) distributed over an active side of the memory die, wherein the plurality of first connecting structures (108) are connected to the plurality of second connecting structures (118, 128) in a one-to-one configuration, and the first tier is electrically coupled to the second tier.
Re: claim 2, Yu discloses in fig. 1 the semiconductor device of claim 1, further comprising: an insulating encapsulation (130), disposed over the first tier and laterally covering the memory die, wherein the insulating encapsulation (130) is a part of the second tier.
Re: claim 3, Yu discloses in fig. 1 the semiconductor device of claim 2, wherein a sidewall of the insulating encapsulation (130) is aligned with a sidewall of the semiconductor die (102) (see also fig. 6).
Re: claim 5, Yu discloses in fig. 1 the semiconductor device of claim 1, wherein the semiconductor die further comprises: a first substrate (102) having a first side and a second side opposite to the first side, the second side being closer to the non-active side of the semiconductor die than the first side is; a first interconnect (within 140), disposed over the first side of the first substrate; a plurality of first through vias (105), penetrating through the first substrate and electrically coupled to the first interconnect (108), a first pitch being between two adjacent first through vias (105) of the plurality of first through vias; a plurality of third connecting structures (105), disposed over the first side of the first substrate and electrically coupled to the plurality of first through vias (105) through the first interconnect; and the plurality of first connecting structures (108), disposed over the second side of the first substrate and electrically coupled to the plurality of first through vias (105), a second pitch being between two adjacent first connecting structures (108) of the plurality of first connecting structures, wherein the first substrate (102) is disposed between the plurality of third connecting structures (150) and the plurality of first connecting structures (108).
Re: claim 6, Yu discloses in fig. 1 the semiconductor device of claim 5, wherein the first pitch is greater than the second pitch (fig. 1).
Re: claim 9, Yu discloses in fig. 1 the semiconductor device of claim 5, the semiconductor die further comprises: a second interconnect (within 104), disposed between and electrically coupling the plurality of first connecting structure (108) and the plurality of first through vias (105).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2021/0066254) (hereinafter, “Yu”) in view of Yu et al. (US 11,581,281) (hereinafter, “Yu ‘281”)
Re: claim 4, Yu discloses in fig. 1 the semiconductor device of claim 1.
Yu does not disclose wherein a sidewall of the memory die is aligned with a sidewall of the semiconductor die.
Yu ‘281 discloses in fig. 6 wherein a sidewall of a memory die (50) is aligned with a sidewall of a semiconductor die (70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the memory die and the semiconductor die with aligned sidewalls since this configuration is merely a design choice that would have been obvious to one of ordinary skill in the art as exemplified by Yu ‘281.
Claims 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2021/0066254) (hereinafter, “Yu”).
Re: claims 7-8, Yu discloses in fig. 1 the semiconductor device of claim 5.
Yu does not disclose expressly wherein the first pitch is less than the second pitch; and wherein the first pitch is substantially equal to the second pitch.
However, dimensional limitations are prime facie obvious unless there is disclosure that the relative dimensions produce new and unexpected results, are for some unobvious purpose or are otherwise critical. See MPEP §2144.04.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 8/28/2026
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