Prosecution Insights
Last updated: October 21, 2026
Application No. 18/664,324

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102
Filed
May 15, 2024
Priority
Mar 21, 2024 — TW 113110615
Examiner
ERDEM, FAZLI
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hon Young Semiconductor Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
934 granted / 1092 resolved
+17.5% vs TC avg
Strong +16% interview lift
Without
With
+15.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
20 currently pending
Career history
1123
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
50.5%
+10.5% vs TC avg
§102
37.7%
-2.3% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1092 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 6-20 in the reply filed on 7/20/2026 is acknowledged. Furthermore, with the response of 7/20/2026, non-elected device claims 1-5 are cancelled. Hence, pending claims 6-20 are examined with this action. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 6-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamada et al. (20160020156). Regarding Claim 6, in Figs. 1-4, Yamada et al. discloses a method for manufacturing a semiconductor structure, comprising: performing an etching process on a top surface of a silicon carbide substrate using an alkaline etching solution (Fig.2, step S20), wherein the alkaline etching solution comprises at least one alkaline substance with a hydroxyl group (see paragraph 0055); after the etching process, performing a grinding process on the top surface of the silicon carbide substrate using a grinding solution comprising hydrogen peroxide and a plurality of silicon dioxide particles (see step S45 in Fig. 2, further see colloidal silica in paragraphs 0058 and 0059 which inherently has hydrogen peroxide and particles); and performing an epitaxial process on the top surface of the silicon carbide substrate to form an epitaxial layer (see step S5 in Fig. 4). Regarding Claim 7, in paragraph 0055 and 0065, a time of the etching process is 2 minutes to 20 minutes, and a temperature of the etching process is 300°C to 600°C ( Regarding Claim 8, in paragraph 0064, the alkaline substance is potassium hydroxide, sodium hydroxide, tetramethylammonium hydroxide, or combinations thereof. Regarding Claim 9, in paragraph 0064, the alkaline substance is potassium hydroxide. Regarding Claim 10, in paragraph 0055, based on a total weight of the alkaline etching solution, a weight of the alkaline substance in the alkaline etching solution is 80 wt.% to 90 wt.%. Regarding Claim 11, in paragraphs 0058 and 0059, an average particle diameter of the silicon dioxide particles is 70 nm to 80 nm. Regarding Claim 12, in paragraphs 0058 and 0059, based on a total weight of the grinding solution, a weight of the silicon dioxide particles is 5 wt.% to 25 wt.%. Regarding Claim 13, in paragraphs 0058, 0059, 0081 and 0085, a grinding depth of the grinding process on the top surface of the silicon carbide substrate is 0.1 µm to 0.2 µm. Regarding Claim 14, in Figs. 1-4 and paragraphs method for manufacturing a semiconductor structure, comprising: performing an etching process on a top surface of a silicon carbide substrate to form a plurality of etching pits (Figs. 3 and 4, step S20), wherein an average maximum width of the etching pits is 30 µm to 50 µm; after the etching process (see paragraph 0057) , performing a grinding process on the top surface of the silicon carbide substrate to reduce the average maximum width of the etching pits (see Figs. 3 and 4 step S40) to 5 µm to 35 µm (see paragraphs 0040, 0081 and 0085); and performing an epitaxial process on the top surface of the silicon carbide substrate to form an epitaxial layer (see Figs. 3 and 4 step S50). Regarding Claim 15, a basal plane dislocation density of the silicon carbide substrate is 5000 times to 30000 times of a basal plane dislocation density of the epitaxial layer (see paragraph 0054). Regarding Claim 16, in paragraph 0054, during the epitaxial process, a conversion rate from a basal plane dislocation to a threading edge dislocation in the epitaxial layer is greater than 99.98%. Regarding Claim 17, in paragraphs 0040, 0081 and 0085, after the grinding process, a bottommost portion of each of the etching pits has a first inclined surface and a second inclined surface connected with each other, and an angle between the first inclined surface and the second inclined surface is 88 degrees to 92 degrees. Regarding Claim 18, in paragraphs 0058 and 0059, the grinding process on the top surface of the silicon carbide substrate is performed using a grinding solution comprising a plurality of silicon dioxide particles, and an average particle diameter of the silicon dioxide particles is 70 nm to 80 nm. Regarding Claim 19, in paragraphs 0058 and 0059, based on a total weight of the grinding solution, a weight of the silicon dioxide particles is 5 wt.% to 25 wt.%. Regarding Claim 20, in paragraphs 0058 and 0059, a grinding depth of the grinding process on the top surface of the silicon carbide substrate is 0.1 µm to 0.2 µm Examiner is including Sumakeris (2005/0064723), Balachandran 20200056302 and Sudarshan (20130143396) as pertinent prior art references that are not relied upon on this rejection but that do disclose surface processing of SiC substrates/wafers to increase BPD to TED conversion rate for surface processed high quality SiC epitaxial wafers. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAZLI ERDEM/Primary Examiner, Art Unit 2812 9/30/2026
Read full office action

Prosecution Timeline

May 15, 2024
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR DEVICE AND AN ELECTRONIC SYSTEM INCLUDING THE SAME
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+15.7%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1092 resolved cases by this examiner. Grant probability derived from career allowance rate.

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