DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I, drawn to Figures 1, 2, 4, and 5 and claims 1-8 and 17-20 in the reply filed on 08/03/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 9-16 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/03/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Joseph (US 20090267238 A1), hereinafter referred to as Joseph238, in view of Liff et al. (US 20200098725 A1). hereinafter referred to as Liff725.
Regarding claim 1: Joseph238 teaches a semiconductor package comprising: a package substrate (Fig. 1A, element 110) including a trench (See Fig. 1A, “If the substrate 110 is a ceramic substrate, then the ceramic substrate 110 can be ground so as to create a space to accommodate the bridge 115.”, para. [0029]); a first chip structure (See Fig. 1A annotated below) including a first buffer chip (bridge 115, “in one embodiment, some of the interposers 120, 122, 124, 130, 132, and 134 and the bridge 115 are semiconductor chips (similar to the semiconductor chip 130 of FIG. 1Bii)”, para. [0019], “the semiconductor chip 130 of FIG. 1Bii can be one of the following: a memory interface chip”, para. [0018]) and a plurality of first semiconductor chips on the first buffer chip (See Fig. 1A annotated below, chips 120-126); and a second chip structure (See Fig. 1A annotated below) including a second buffer chip and a second semiconductor chip on the second buffer chip (“memory interface chips and/or a voltage regulation chip such as silicon package interposer layers 132 and 130 (and additional layers as needed but not shown)”, para. [0021], buffer chip 132, second chip 138), wherein one of the first and second chip structures is on the trench, the other one of the first and second chip structures is on a top surface of the package substrate (See Fig. 1A, bridge 115 is in/on the trench, interposers 130, 132, and 134 are on the top surface of the substrate).
Joseph238 does not explicitly teach that a first physical layer (PHY) region of the first buffer chip overlaps with a second PHY region of the second buffer chip in a direction perpendicular to the top surface of the package substrate.
Liff725 teaches an interposer with memory control logic and a physical PHY layer (the interposer 120 may include memory control logic 150”, para. [0036], “The memory control logic may include a physical layer (PHY) logic that is at the edge of the memory control logic.”, para. [0054]). Liff725 also teaches embodiments where two memory control regions overlap (See Fig. 7, “memory control logics 750, 745, and 760 may each be similar to memory control logic 150, while in other embodiments the memory control logics 745/750/760 may be disaggregated elements of a single memory control logic.”, para. [0052]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that the overlapping memory control logic regions with corresponding physical layers taught by Liff725 could be substituted into the device taught Joseph238 to arrive at the claimed invention. Since Joseph238 teaches that both interposer 130 and bridge 115 may be memory interface chips, and that multiple memory interface chips may be included in the same device, such a substitution would have predictable results. Furthermore, overlapping memory control layers including physical layers and their functions were well known in the art.
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Fig. 1A from Joesph238 annotated: Bridge 115 may be a memory interface (buffer) chip, interposer 130 may also be a memory interface (buffer) chip. Second chip structure includes all chips within the solid black box.
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Fig. 7 taken from Liff725: Memory regions and corresponding physical layers 745 and 750 are depicted as overlapping.
Regarding claim 2: In addition to the reasoning used to reject claim 1, Joseph238 teaches wherein one of the first and second buffer chips is in the trench, and the other one of the first and second buffer chips is on the top surface of the package substrate. (See Fig. 1A above, first buffer chip 115 is in the trench while second buffer chip 130 is on the top surface of the substrate).
Regarding claim 3: In addition to the reasoning used to reject claim 1, Liff725 teaches a connection terminal in contact with the first and second PHY regions. (See Fig 7 above, solder bumps 725).
Regarding claim 4: In addition to the reasoning used to reject claim 3, Liff725 does not explicitly teach, with regards to the embodiment shown in figure 7, that the first PHY region includes first through via therein, the second PHY region includes second through via therein, and the first through via and the second through via are in contact with the connection terminal.
However, Liff teaches connection paths including through-vias in several other embodiments (See at least Fig. 9, “conductive pathways 945, which may generally be similar to conductive pathways 103/107/111/109/113/117/etc., and which may include one or more vias, traces, or solder bumps.)
It would have been obvious to a person of ordinary skill in art before the effective filing date of the claimed invention, that the conductive pathways shown in Figure 9 of Liff725 could be substituted into the device shown in Figure 7 of Liff725 to arrive at the claimed invention. A person of ordinary skill in the art would understand that conductive pathways must be present in the device shown in Figure 7, and could look to other parts of the disclosure, such as the description of Figure 9 (paras. 59-60), to see that the conductive pathways include through-vias in addition to solder bumps. Furthermore, through vias and solder bumps, along with their functions, are well known in the art and the results would be predictable.
Claim(s) 5-6 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Joseph (US 20090267238 A1), hereinafter referred to as Joseph238, in view of Liff et al. (US 20200098725 A1) hereinafter referred to as Liff725 and Bertrand et al. (US 20210257277 A1) hereinafter referred to as Bertrand277.
Regarding claim 5: In addition to the reasoning used to reject claim 1, Joseph238 and Liff725 do not teach a thermal transfer material layer on a second semiconductor chip and a heat dissipation member on the thermal transfer material layer. Bertrand277 teaches a thermal transfer material layer (See Fig. 5A thermal conductive vias 564a) on a semiconductor chip (Fig. 5A element 527); and a heat dissipation member (See Fig. 5A thermal block 562) on the thermal transfer material layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to add a thermal transfer material and a heat dissipation material to the top of the second semiconductor chip in the device taught by Joseph238 (element 138, see Fig. 1A annotated above) to improve its heat dissipation characteristics and arrive at the claimed invention of claim 5. Since the heat transfer materials, heat dissipation member, and their functions were well-known in the art, such a modification could be made with a reasonable expectation of success.
Regarding claim 6: In addition to the reasoning used to reject claim 5, Liff725 and Joseph238 do not teach that the top surface of the first chip structure is on the same plane as a top surface of the heat dissipation member. Bertrand277 teaches a top surface of the first chip structure is on the same plane as a top surface of the heat dissipation member. (See Fig. 5A thermal block 562 is shown to be co-planar with HBM die stack 540, 542, and 544).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that when substituting in the thermal block on top of the second semiconductor chip of the device taught by Joseph238, that the height of the thermal block would be selected such that the top surface of the thermal block would be co-planar with the top surfaces of the surrounding chip stacks (top surface of chips 138 and 126, see Fig. 1A annotated above). This would strengthen the overall structure of the device and allow for more equal heat distribution to any additional heat dissipation materials above the device.
Regarding claim 17: Joseph238 teaches a semiconductor package comprising: a package substrate (Fig. 1A, element 110) including a trench (See Fig. 1A, “If the substrate 110 is a ceramic substrate, then the ceramic substrate 110 can be ground so as to create a space to accommodate the bridge 115.”, para. [0029]); a first chip structure on the package substrate (See Fig. 1A annotated above), the first chip structure including a first buffer chip (bridge 115, “in one embodiment, some of the interposers 120, 122, 124, 130, 132, and 134 and the bridge 115 are semiconductor chips (similar to the semiconductor chip 130 of FIG. 1Bii)”, para. [0019], “the semiconductor chip 130 of FIG. 1Bii can be one of the following: a memory interface chip”, para. [0018]), and a plurality of first semiconductor chips on the first buffer chip (See Fig. 1A above); a second chip structure on the package substrate (See Fig. 1A above), the second chip structure including a second buffer chip (“memory interface chips and/or a voltage regulation chip such as silicon package interposer layers 132 and 130 (and additional layers as needed but not shown)”, para. [0021]), and a plurality of second semiconductor chips on the second buffer chip (See Fig. 1A above), one of the first and second buffer chips is in the trench, and the other one of the first and second buffer chips is on the top surface of the package substrate. (See Fig. 1A, bridge 115 is in/on the trench, interposers 130, 132, and 134 are on the top surface of the substrate).
Joseph238 does not explicitly teach that a first physical layer (PHY) region of the first buffer chip overlaps with a second PHY region of the second buffer chip in a direction perpendicular to the top surface of the package substrate.
Liff725 teaches an interposer with memory control logic and a physical PHY layer (“the interposer 120 may include memory control logic 150”, para. [0036], “The memory control logic may include a physical layer (PHY) logic that is at the edge of the memory control logic.”, para. [0054]). Liff725 also teaches embodiments where two memory control regions overlap (See Fig. 7, “memory control logics 750, 745, and 760 may each be similar to memory control logic 150, while in other embodiments the memory control logics 745/750/760 may be disaggregated elements of a single memory control logic.”, para. [0052]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that the overlapping memory control logic regions with corresponding physical layers taught by Liff725 could be substituted into the device taught Joseph238 to arrive at the claimed invention. Since Joseph238 teaches that both interposer 130 and bridge 115 may be memory interface chips, and that multiple memory interface chips may be included in the same device, such a substitution would have predictable results. Furthermore, overlapping memory control layers including physical layers and their functions were well known in the art.
Joseph238 and Liff725 do not teach a thermal transfer material layer on the second chip structure; a first heat dissipation member on the thermal transfer material layer; a molding layer on the package substrate, the molding layer on the first chip structure and the first heat dissipation member; and a second heat dissipation member on the molding layer.
Bertrand277 teaches thermal transfer material layer (See Fig. 5A thermal conductive vias 564a) on a semiconductor chip (Fig. 5A element 527); and a first heat dissipation member (See Fig. 5A thermal block 562) on the thermal transfer material layer; and a second heat dissipation member (integrated heat spreader 534).
Bertrand teaches in a separate embodiment (See Fig. 4A) a molding layer on the package substrate, the molding layer on the first chip structure and the first heat dissipation member (“In embodiments, the thermal block 439 may include a thermally conductive mold material that may be used to conduct thermal energy from the base die 426 to the TIM 432”, para. [0040]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to add a thermal transfer material, first heat dissipation member, a molding layer, and a second heat dissipation material to the top of the second semiconductor chip (See Fig. 1A annotated above, element 138) taught by Joseph238 and Liff725 by known methods to arrive at the claimed invention of claim 17. In this case, the heat dissipation characteristics of the device would be improved. Since the thermal transfer material, the heat dissipation members, and their functions were well-known int the art, such a modification would have predictable results.
Regarding claim 18: In addition to the reasoning used to reject claim 17, Liff725 and Joseph238 do not teach that the top surface of the first chip structure is on the same plane as a top surface of the first heat dissipation member. Bertrand277 teaches a top surface of the first chip structure is on the same plane as a top surface of the first heat dissipation member. (See Fig. 5A thermal block 562 is shown to be co-planar with HBM die stack 540, 542, and 544).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that when substituting in the thermal block on top of the second semiconductor chip of the device taught by Joseph238, that the top surface of the thermal block would be co-planar with the top surfaces of the surrounding chip stacks (top surface of chips 138 and 126, see Fig. 1A annotated above). This would strengthen the overall structure of the device and allow for more equal heat distribution to any additional heat dissipation materials above the device.
Regarding claim 19: In addition to the reasoning used to reject claim 17, Joseph238 teaches the first memory chips are memory chips (“the semiconductor chip 126 is a memory chip.”, para. [0045], “some of the interposers 120, 122, 124, 130, 132, and 134 and the bridge 115 are semiconductor chips (similar to the semiconductor chip 130 of FIG. 1Bii)”, para. [0019], “In one embodiment, the semiconductor chip 130 of FIG. 1Bii can be one of the following: a memory interface chip”, para. [0018]), and the second semiconductor chip is a processor chip (“die stacks in FIG. 1A may serve other functions than microprocessor and memory or cache such as memory interface die, application specific integrated circuit die”, para. [0045], In the specification of the instant case, application specific integrated circuit die is listed as an example of a processor, see para. [0042]).
Claim(s) 7-8 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Joseph (US 20090267238 A1), hereinafter referred to as Joseph238, in view of Liff et al. (US 20200098725 A1) hereinafter referred to as Liff725, Bertrand et al. (US 20210257277 A1) hereinafter referred to as Bertrand277, and Chen et al. (US 20220310470 A1) hereinafter referred to as Chen470.
Regarding claim 7: In addition to the reasoning used to reject claim 5, Liff725 and Joseph238 do not teach the use of a dummy chip. Bertrand277 teaches a dummy chip (Fig. 3A, dummy die 338), and a connection terminal between the dummy chip and semiconductor chip. (“In embodiments, the dummy die 338 may be directly coupled with the base die 326 using a legacy interconnect technology, solder balls, micro bumps, and the like, that allow for high thermal conductivity. In embodiments, the dummy die 338 may be directly coupled using an adhesive designed to withstand a range of thermal activity produced by the base die 326.”, para. [0035]).
Bertrand277 does not teach that a dummy chip is in between the second semiconductor chip and the thermal transfer material layer.
Chen470 teaches a stack of thermally conductive dummy chips (See Fig. 14, “multiple heat dissipation dies 94 (e.g., a lower heat dissipation die 94A, a middle heat dissipation die 94B, and an upper heat dissipation die 94C) are stacked”, para. [0059]).
It would have been obvious to a person of ordinary skill in art before the effective filing date of the claimed invention, that the bonding methods of the dummy die in the device shown in Fig. 3A of Bertrand277 could be substituted into the dummy chip stack taught by Chen470, and that the resulting dummy die stack could be placed on top of the second semiconductor chip of Joseph238 (See Fig. 1A annotated above, element 138) to arrive at the claimed invention. Including additional dummy dies to fill the gap between the second semiconductor chip and the plane of top of the first semiconductor chip stack would also improve the strength and structural integrity of the device. Furthermore, the dummy dies and the means of attaching the dummy dies are well-known in the art and the results would be predictable.
Regarding claim 8: In addition to the reasoning used to reject claim 5, Liff725 and Joseph238 do not teach the use of a dummy chip. Bertrand277 teaches a dummy chip (Fig. 3A, dummy die 338), and an adhesive layer between the dummy chip and the second semiconductor chip. (“In embodiments, the dummy die 338 may be directly coupled using an adhesive designed to withstand a range of thermal activity produced by the base die 326.”, para. [0035]).
Bertrand277 does not teach that a dummy chip is in between the second semiconductor chip and the thermal transfer material layer.
Chen470 teaches a stack of thermally conductive dummy chips (See Fig. 14, “multiple heat dissipation dies 94 (e.g., a lower heat dissipation die 94A, a middle heat dissipation die 94B, and an upper heat dissipation die 94C) are stacked”, para. [0059]).
It would have been obvious to a person of ordinary skill in art before the effective filing date of the claimed invention, that the bonding methods of the dummy die in the device shown in Fig. 3A of Bertrand277 could be substituted into the dummy chip stack taught by Chen470, and that the resulting dummy die stack could be placed on top of the second semiconductor chip of Joseph238 (See Fig. 1A annotated above, element 138) to arrive at the claimed invention. Including additional dummy dies to fill the gap between the second semiconductor chip and the plane of top of the first semiconductor chip stack would also improve the strength and structural integrity of the device. Furthermore, the dummy dies and the means of attaching the dummy dies are well-known in the art and the results would be predictable.
Regarding claim 20: In addition to the reasoning used to reject claim 17, Bertrand277 teaches a dummy chip (See Fig. 3A, dummy die 338).
Bertrand277 does not teach that a dummy chip is in between the second semiconductor chip and the thermal transfer material layer.
Chen470 teaches a stack of thermally conductive dummy chips (See Fig. 14, “multiple heat dissipation dies 94 (e.g., a lower heat dissipation die 94A, a middle heat dissipation die 94B, and an upper heat dissipation die 94C) are stacked”, para. [0059]).
It would have been obvious to a person of ordinary skill in art before the effective filing date of the claimed invention, that the dummy chip stack taught by Chen470 could be placed on top of the second semiconductor chip of Joseph238 (See Fig. 1A annotated above, element 138) to arrive at the claimed invention. Including additional dummy dies to fill the gap between the second semiconductor chip and the plane of the first semiconductor chip stack would also improve the strength and structural integrity of the device. Furthermore, the dummy dies and the means of attaching the dummy dies are well-known in the art and the results would be predictable.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure: Collins (US 20200075567 A1) teaches two overlapping memory die structures with a dummy die for thermal transfer. Yun et al. (US 20180026013 A1) teaches two memory buffer regions with overlapping physical layers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
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/ROBERT L STEWART/ Examiner, Art Unit 2898
/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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