Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 15, 2024 was filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshimizu et al. (US 2020/0303408).
Regarding Claim 1:
Yoshimizu discloses a semiconductor storage device comprising:
a substrate (substrate, See fig. 1, ref. no. 19 and paragraphs 16-17);
a first wiring layer (the back gate and the metal pad, See fig. 1, ref. nos. 14, 47, paragraphs 16 and 21);
a second wiring layer (polysilicon semiconductor layer, See fig. 1, ref. no. 12, paragraphs 16 and 40) disposed between the substrate and the first wiring layer;
a memory cell array layer (the layer between the top surfaces of the insulator and the metal pads and the bottom surfaces of the polysilicon semiconductor layer, the back-gate insulator, the back-gate electrode, the passivation film, and the metal pad, See fig. 1, ref. nos. 12, 13, 14, 16, 41, 47, 48, paragraphs 16 and 21) disposed between the substrate and the second wiring layer; and
a first insulating layer (passivation film made silicon oxide, See fig. 1, ref. no. 48 and paragraph 21) disposed on a side (top side of the back-gate electrode and the metal pad, See fig. 1, ref. nos. 14 and 47) opposite to the substrate with respect to the first wiring layer,
wherein the memory cell array layer includes
a plurality of first conductive layers (word lines stacked in the Z-direction, See figs. 1-2, ref. no. WL, paragraphs 19 and 22-23) arranged in a first direction (Z-direction, See fig. 1) intersecting a surface of the substrate (top surface of the substrate, See fig. 1, ref. no. 19),
a first semiconductor layer (channel semiconductor layer of the columnar portion, See figs. 1-2, ref. no. CL, fig. 2, ref. no. 55, paragraphs 19 and 24) extending in the first direction and facing the plurality of first conductive layers (the channel semiconductor layer extends in the Z-direction and faces the word lines, See figs. 1-2, ref. no. CL, fig. 2, ref. no. WL and 55),
a first charge storage layer (charge storage layer, See fig. 2, ref. no. 53 and paragraph 24) disposed between the plurality of first conductive layers and the first semiconductor layer (the charge storage layer is disposed between the wordlines and the channel semiconductor layer, See fig. 2, ref. no. WL, 53, and 55),
a first contact (via-plug, See fig. 1, ref. no. 46 and paragraph 21) extending in the first direction, and
a second contact (contact plug, See fig. 1, ref. no. 24 and paragraph 19) extending in the first direction,
the second wiring layer including a second conductive layer (the polysilicon semiconductor layer is electrically connected to channel semiconductor layer at the top end of the channel semiconductor layer, See fig. 1, ref. nos. CL, 12, paragraphs 19 and 45) electrically connected to one end of the first semiconductor layer,
the first wiring layer includes
a first electrode (the metal pad is electrically connected to the via-plug, See fig. 1, ref. nos. 46, 47, and paragraph 21) electrically connected to the first contact, and
a second electrode (the back gate electrode is electrically connected to the contact plug, See fig. 1, ref. nos. 14, 24, and paragraph 21) electrically connected to the second contact,
at least a part of a surface of the first electrode (the bottom surface of the metal pad, See fig. 1, ref. no. 47) on a substrate side and at least a part of a surface of the second electrode (the bottom surface of the lowest section of the back gate, See fig. 1, ref. no. 14) on the substrate side are closer to the substrate than a surface of the second conductive layer (top surface of the polysilicon semiconductor layer, See fig. 1, ref. no. 12) on the side opposite to the substrate in the first direction (the bottom surface of the metal pad and the bottom surface of the lowest section of the back gate are closer to the substrate than the top surface of the polysilicon semiconductor layer, See fig. 1, ref. nos. 12, 14, 47)
a surface of the first electrode (top surface of the metal pad in the opening, See fig. 1, ref. nos. P and 47) on the side opposite to the substrate includes a region not covered with the first insulating layer, and
a surface of the second electrode (top surface of the back gate electrode is covered by the passivation film, See fig. 1, ref. nos. 14, 48 and paragraph 21) on the side opposite to the substrate is entirely covered with the first insulating layer.
Regarding Claim 4:
Yoshimizu wherein the second electrode includes
a first portion (the lowest horizontal section of the back-gate electrode is in contact with the end of the contact plug, See fig. 1, ref. nos. 14 and 24) in contact with one end portion of the second contact,
a second portion (the highest horizontal section of the back-gate electrode, See fig. 1, ref. no. 14) disposed at a position that: (a) does not overlap with the first portion as viewed from the first direction (the highest horizontal section of the back-gate electrode does not overlap with the lowest horizontal section, See fig. 1, ref. no. 14), and (b) is further from the substrate with respect to the second conductive layer (the highest horizontal section is located further from the substate than the lowest horizontal section, See fig. 1, ref. nos. 14 and 19), and a third portion (the middle section of the back-gate electrode connects the lowest horizontal section to the highest horizontal section, See fig. 1, ref. no. 14) connected to the first portion and the second portion and extending from the first portion to the second portion.
Regarding 5:
Yoshimizu a bonding wire (wire bonding can be connected to the metal pad, See paragraph 21) in contact with the first electrode.
Regarding 6:
Yoshimizu discloses wherein the second conductive layer contains polycrystalline silicon (polysilicon semiconductor layer, See fig. 1, ref. no. 12, paragraph 40. The examiner notes the polysilicon is understood to refer to polycrystalline silicon).
Regarding Claim 17:
Yoshimizu discloses wherein the first charge storage layer is formed of silicon nitride, (the charge storage layer is a silicon nitride film, See paragraph 24)
Regarding Claim 18:
Yoshimizu discloses a tunnel insulating film (tunnel insulator, See fig. 2, ref. no. 54 and paragraph 24) and a block insulating film (block insulator, See fig. 2, ref. no. 52 and paragraph 24), wherein the first charge storage layer is disposed between the tunnel insulating film and the block insulating film (the charge storage layer is disposed between the tunnel insulator and the block insulator, See fig. 2, ref. nos. 52, 53, 54, and paragraph 24).
Allowable Subject Matter
Claims 2-3 and 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to dependent claim 2, the disclosures and illustrations of Yoshimizu as discussed above fail to teach and/or suggest the semiconductor storage device further comprises a first memory plane and a second memory plane arranged in a second direction intersecting the first direction, wherein, in the first memory plane, the memory cell array layer includes the plurality of first conductive layers, the first semiconductor layer, and the first charge storage layer, in the second memory plane, the memory cell array layer includes a plurality of third conductive layers separated from the plurality of first conductive layers in the second direction and arranged in the first direction, a second semiconductor layer extending in the first direction and facing the plurality of third conductive layers, and a second charge storage layer disposed between the plurality of third conductive layers and the second semiconductor layer, and wherein the second electrode is disposed between the first memory plane and the second memory plane. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Yoshimizu to teach and/or suggest the limitations of claim 2. Therefore, claim 2 includes allowable subject matter. Claim 3 depends from claim 2, and thus, includes the subject matter of claim 2. Therefore, claim 3 includes allowable subject matter.
With respect to dependent claim 7, the disclosures and illustrations of Yoshimizu as discussed above fail to teach and/or suggest the first wiring layer includes wiring electrically connected to the second conductive layer. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Yoshimizu to teach and/or suggest the limitations of claim 7. Therefore, claim 7 includes allowable subject matter.
With respect to independent claim 8, the disclosures and illustrations of Yoshimizu disclose a semiconductor storage device comprising:
a substrate (substrate, See fig. 1, ref. no. 19 and paragraphs 16-17);
a first wiring layer (the back gate and the metal pad, See fig. 1, ref. nos. 14, 47, paragraphs 16 and 21);
a second wiring layer (polysilicon semiconductor layer, See fig. 1, ref. no. 12, paragraphs 16 and 40) disposed between the substrate and the first wiring layer; and
a memory cell array layer (the layer between the top surfaces of the insulator and the metal pads and the bottom surfaces of the polysilicon semiconductor layer, the back-gate insulator, the back-gate electrode, the passivation film, and the metal pad, See fig. 1, ref. nos. 12, 13, 14, 16, 41, 47, 48, paragraphs 16 and 21) disposed between the substrate and the second wiring layer, wherein the memory cell array layer includes a plurality of first conductive layers (word lines stacked in the Z-direction, See figs. 1-2, ref. no. WL, paragraphs 19 and 22-23) arranged in a first direction (Z-direction, See fig. 1) intersecting a surface of the substrate (top surface of the substrate, See fig. 1, ref. no. 19), a first semiconductor layer (channel semiconductor layer of the columnar portion, See figs. 1-2, ref. no. CL, fig. 2, ref. no. 55, paragraphs 19 and 24) extending in the first direction and facing the plurality of first conductive layers (the channel semiconductor layer extends in the Z-direction and faces the word lines, See figs. 1-2, ref. no. CL, fig. 2, ref. no. WL and 55), a first charge storage layer (charge storage layer, See fig. 2, ref. no. 53 and paragraph 24) disposed between the plurality of first conductive layers and the first semiconductor layer (the charge storage layer is disposed between the wordlines and the channel semiconductor layer, See fig. 2, ref. no. WL, 53, and 55), a first contact (via-plug, See fig. 1, ref. no. 46 and paragraph 21) extending in the first direction, and a second contact (contact plug, See fig. 1, ref. no. 24 and paragraph 19) extending in the first direction,
the second wiring layer includes a second conductive layer (the polysilicon semiconductor layer is electrically connected to channel semiconductor layer at the top end of the channel semiconductor layer, See fig. 1, ref. nos. CL, 12, paragraphs 19 and 45) electrically connected to one end of the first semiconductor layer, and
the first wiring layer includes a first electrode (the metal pad is electrically connected to the via-plug, See fig. 1, ref. nos. 46, 47, and paragraph 21) electrically connected to the first contact.
Yoshimizu fails to teach or suggest the second wiring layer includes a first conductive member connected to one end of the second contact and having lengths in (i) a second direction intersecting the first direction and (ii) a third direction intersecting the first direction and the second direction that are smaller than lengths of the second conductive layer in the second direction and the third direction, respectively, and the first wiring layer includes another conductive layer separated from the first conductive member in the first direction and entirely covering a surface of the first conductive member on the side opposite to the substrate. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Yoshimizu to teach and/or suggest the limitations of claim 8. Therefore, claim 8 is allowable. Claims 9-16 and 19-20 depends from claim 8, and thus, includes the subject matter of claim 8. Therefore, claim 9-16 and 19-20 are allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0398996 to Parekh discloses 3D NAND flash memory devices (See figs. 1, 3-6, and paragraphs 28, 78, 81, 84, and 89)
US 2024/0242765 to Yoon et al. discloses a bonding vertical NAND structure (See fig. 9 and paragraphs 93-94).
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/B.S./Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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