DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (claim 1-7) in the reply filed on 11/20/2025 is acknowledged.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/15/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yabuuchi (US 10,541,028), and further in view of Lai et al. (US 2020/0105671 A1).
Regarding claim 1, Yabuuchi teaches an integrated circuit comprising:
a ternary content-addressable memory (TCAM) cell on a front side of a substrate (Fig. 20 and Fig. 22, TCAM cell on a front side of a substrate), the TCAM cell including a first cell storing a first value, a second cell storing a second value, and a comparison circuit connected with the first cell and the second cell (Fig. 1, first memory cell MCX and second memory cell MCY, and comparison circuit 13); and
a frontside wiring layer above the TCAM cell in the vertical direction, the frontside wiring layer including a bit line connected with the first cell and the second cell, a complementary bit line connected with the first cell and the second cell, and a match line connected with the comparison circuit (Fig. 22, the bit line BL0A and complementary bit line /BL)A and the matching line ML are in the frontside wiring layer above the TCAM cell).
Yabuuchi is silent in teaching a backside via extending through the substrate in a vertical direction with respect to the substrate; a backside wiring layer on a back side of the substrate, the backside wiring layer including at least one backside power rail configured to transmit a supply voltage to the TCAM cell through the backside via.
Lai teaches a backside via extending through the substrate in a vertical direction with respect to the substrate; a backside wiring layer on a back side of the substrate, the backside wiring layer including at least one backside power rail configured to transmit a supply voltage to the TCAM cell through the backside via (Fig. 2C, backside via TSV extending through the substrate 203 in a vertical direction with respect to the substrate. A backside wiring layer on the backside of the substrate transmit supply voltage VSS to the memory cell through the backside. the backside wiring layer 408 on the back of side of the substrate).
It would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to Lai’s backside wiring for the supplying a voltage to the memory cell in order to have a smaller integrated circuit and more efficient power rail structure to help reduce the size for the memory device.
Regarding claim 2, Yabuuchi and Lai further teach the integrated circuit of claim 1, wherein the supply voltage corresponds to a ground voltage, and the at least one backside power rail is configured to transfer the ground voltage to the TCAM cell through the backside via (Lai teaches the backside wiring supplies a ground voltage VSS to the memory cell).
Regarding claim 3, Lai further teaches the integrated circuit of claim 2, wherein the at least one backside power rail comprises a plurality of backside power rails, the plurality of backside power rails extending in a first direction, the plurality of backside power rails being spaced apart from each other in a second direction, the second direction crossing the first direction (Fig. 2C).
Regarding claim 4, Yabuuchi further teaches the integrated circuit of claim 2, wherein the frontside wiring layer comprises a frontside power rail configured to transfer a power supply voltage to the TCAM cell (Fig. 20, frontside power rail VSS).
Regarding claim 5, Yabuuchi further teaches the integrated circuit of claim 1, wherein the frontside wiring layer comprises: a search line connected with the comparison circuit (Fig. 22, SL0); and a complementary search line connected with the comparison circuit (Fig. 22, /SL0), and
wherein the comparison circuit is configured to: compare search values with the first value and the second value, the search values being input to the search line and the complementary search line; and output, through the match line, a result of the comparison of the search values with the first value and the second value (Col. 7, lines 34-55).
Regarding claim 6, Yabuuchi further teaches the integrated circuit of claim 1, wherein the frontside wiring layer comprises a word line connected with the first cell and the second cell (Fig. 20, WL0 and WL1).
Regarding claim 7, Yabuuchi and Lai further teaches the integrated circuit of claim 1, wherein the at least one backside power rail extends in a first direction (Lai teaches the power rail extends in a first direction, Fig. 2C), and the frontside wiring layer comprises: a first frontside wiring layer including the bit line and the complementary bit line, the first frontside wiring layer extending in a second direction, the second direction crossing the first direction (bit line BL0A and complementary bit line /BL0A are extending in second direction); and a second frontside wiring layer above the first frontside wiring layer in the vertical direction, the second frontside wiring layer including a plurality of word lines and the match line that extend in the first direction ( plurality of word line WL and match line ML are in a second frontside wiring above the first wiring layer in a vertical direction)).
Relevant reference:
Chen et al. (US 2024/0154015) teaches a backside wiring layer (Fig. 6B, 408) which provides power to the memory cells (SRAM or CAM cells). The backside wiring layer connects to the frontside of the substrate using the Vias 416s.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824