DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 05/15/2024.
Claims 1-18 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 05/15/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Foreign Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
4. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
5. Claims 1 and 18 are objected to because of the following informalities:
In claim 1, the second line from the bottom, and in claim 18, the last line, the phrases “un upper surface” should be changed to “ an upper surface” to correct typo errors.
In claim 18, line 11, the limitation “a second conductivity type” should be changed to -- the second conductivity type – since “the second conductivity type” already being defined at line 5.
In claim 18, the colon mark “:” at the end of line 13 should be changed to a semicolon “;”.
Appropriate correction(s) is/are required.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1, and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morimoto (US 10,892,363)
Regarding claim 1, Morimoto discloses a semiconductor device being divided into an active region (see figs. 1, 8, and the annotated drawing below; see also col. 2, line 55 – col. 3, line 6), a first termination region surrounding the active region, and a second termination region surrounding the first termination region in a plan view, the semiconductor device comprising:
a semiconductor substrate 1 having a first main surface (upper surface) and a second main surface (lower surface) that is a main surface opposite to the first main surface, wherein
the semiconductor substrate 1 includes
a drift layer of a second conductivity type (n-- drift layer; col. 3, lines 35-41),
a plurality of first termination semiconductor layers 5 of a first conductivity type (p-type) provided in a front surface layer of the drift layer on the first main surface side in the first termination region, and
a second termination semiconductor layer 6 of the second conductivity type (n-type) provided in the surface layer of the drift layer on the first main surface side at an end portion of the semiconductor substrate 1 in the second termination region, the semiconductor device further comprising:
a first insulating layer (see annotated drawing below) provided on the first main surface in the first termination region;
a plurality of first termination electrode layers 10 provided on the first main surface and electrically connected to the plurality of first termination semiconductor layers 5 through openings 8b of the first insulating layer;
a second termination electrode layer 11 provided on the first main surface and electrically connected to the second termination semiconductor layer 6;
a second insulating layer (see annotated drawing) provided on the first main surface, having one end thereof in contact with outermost one of the plurality of first termination semiconductor layers 5 among the plurality of first termination semiconductor layers 5, and having an other end thereof in contact with the second termination semiconductor layer 6; and
a sealing material 12 &17 in direct contact with un upper surface of the second insulating layer.
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Regarding claim 16, Morimoto discloses the semiconductor device according to claim 1, wherein an upper surface of the second insulating layer is flat, and a plurality of third insulating layers 12 are discretely provided on the upper surface of the second insulating layer. See fig. 8.
Regarding claim 17, Morimoto discloses the semiconductor device according to claim 1, wherein the semiconductor substrate 1 includes an active region semiconductor layer 4 of the first conductivity type (p-type) provided in the front surface layer of the drift layer on the first main surface side in the active region, the semiconductor device further comprising an active region electrode layer 9 provided on the first main surface and electrically connected to the active region semiconductor layer 4, wherein an upper surface of the first insulating layer has convex portions at least between the active region electrode layer and the first termination electrode layer, and between the adjacent first termination electrode layers. See fig. 8.
Regarding claim 18, Morimoto discloses a method of manufacturing a semiconductor device being divided into an active region (see figs. 1, 8, and the annotated drawing below; see also col. 2, line 55 – col. 3, line 6), a first termination region surrounding the active region, and a second termination region surrounding the first termination region in a plan view, the method of manufacturing comprising:
preparing a semiconductor substrate 1 having a drift layer of a second conductivity type (n-type, col. 3, lines 35-41) and having a first main surface (upper surface) and a second main surface (lower surface) that is a main surface opposite to the first main surface;
forming a plurality of first termination semiconductor layers 5 of a first conductivity type (p-type) provided in a front surface layer of the drift layer on the first main surface side in the first termination region;
forming a second termination semiconductor layer 6 of the second conductivity type (n-type) provided in the surface layer of the drift layer on the first main surface side at an end portion of the semiconductor substrate 1 in the second termination region;
forming a first insulating layer (see the annotated drawing above) provided on the first main surface in the first termination region;
forming a plurality of first termination electrode layers 10 provided on the first main surface and electrically connected to the plurality of first termination semiconductor layers 5 through openings 8b of the first insulating layer;
forming a second termination electrode layer 11 provided on the first main surface and electrically connected to the second termination semiconductor layer 6;
forming a second insulating layer (see annotated drawing) provided on the first main surface, having one end thereof in contact with outermost one of the plurality of first termination semiconductor layers 5 among the plurality of first termination semiconductor layers 5, and having an other end thereof in contact with the second termination semiconductor layer 6; and
sealing an upper surface of the second insulating layer with a sealing material 12 & 17.
Allowable Subject Matter
8. Claims 2-15 are allowable.
Claims 2-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed semiconductor device (in addition to the other limitations in the claim) wherein the upper surface of the second insulating layer has a concave-convex region being a concave-convex shape in cross-sectional view.
Conclusion
9. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 June 24, 2026
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