Prosecution Insights
Last updated: April 19, 2026
Application No. 18/664,567

SEMICONDUCTOR LEADFRAME PACKAGES AND RELATED METHODS

Non-Final OA §102
Filed
May 15, 2024
Examiner
LEE, PETE T
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Components Industries LLC
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
85%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allow Rate
578 granted / 773 resolved
+6.8% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
33 currently pending
Career history
806
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.8%
+16.8% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
12.2%
-27.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 773 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions Applicant’s election without traverse of claims 1-17 in the reply filed on 01/21/26 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim (s) 1-8 and 10-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura (JP 2013254801A). Regarding claim 1, Nakamura discloses a lead frame (Fig.1b) for a semiconductor package, the lead frame comprising: a die attach pad (1;Fig.6) comprising a swag area (8); and one or more leads (1c;Fig.6); wherein the swag area comprises an alternating pattern (see 7,and 8s alternating) therein comprising at least two raised features (see 8 on both sides of 7 each have raised features 11 in Fig.5) , each of the at least two raised features configured to support a clamping finger (see two fingers 5) during a wire bonding process (clamping fingers 5 clamp down on 1 during wire bonding). Regarding claim 2, Nakamura discloses wherein the swag area extends along two opposing sides of the die attach pad (both grooves 8 extend on left and right sides of 1; Fig.1). Regarding claim 3, Nakamura discloses, in Fig.1b, wherein the alternating pattern is located in a first largest planar surface (left planar surface of 1a) of the swag area and located in a second largest planar surface (right planar surface of 1a) of the swag area opposing the first largest planar surface. Regarding claim 4, Nakamura discloses wherein the alternating pattern comprises at least two downset features (see plurality of conical groves in Fig.9e) in combination with the at least two raised features (left and right 8). Regarding claim 5, Nakamura discloses wherein the at least two downset features comprise corners, the corners comprising a substantially 90-degree angle (see Fig.9b where 8 has two features making a corner). Regarding claim 6, Nakamura discloses wherein the at least two downset features comprise corners (see 8 in Fig.9e), the corners comprising a rounded shape (see rounded corner 8 in Fig.9e). Regarding claim 7, Nakamura discloses wherein the at least two downset features comprise corners with rounded edge (see rounded corner 8 in Fig.9e). . Regarding claim 8, Nakamura discloses wherein the at least two downset features comprising a mold lock pattern formed therein (see male-female locking pattern between 3 and 8;Fig.5). Regarding claim 10, Nakamura discloses leadframe for a semiconductor package, the leadframe (see Fig.1b) comprising: a die attach pad (1) comprising a swag area (8); and one or more leads (1c); wherein the swag area comprises an alternating pattern of indentations therein (see 7,and 8s alternating). Regarding claim 11, Nakamura discloses at least two raised features (see 8 on both sides of 7 each have raised features 11 in Fig.5) , of the alternating pattern of indentations (8;Fig.5) are configured to engage with a clamping finger during a wire bonding process (clamping fingers 5 clamp down on 1 during wire bonding). Regarding claim 12, Nakamura discloses wherein the swag area extends along two opposing sides of the die attach pad (both grooves 8 extend on left and right sides of 1; Fig.1), wherein the alternating pattern is located in a first largest planar surface (left planar surface of 1a) of the swag area and located in a second largest planar surface (right planar surface of 1a) of the swag area opposing the first largest planar surface. Regarding claim 13, Nakamura discloses wherein the alternating pattern of indentations (8) comprises at least two downset features (see plurality of conical groves in Fig.9e) in combination with the at least two raised features (left and right 8). Regarding claim 14, Nakamura discloses wherein the at least two downset features comprise corners, the corners comprising a substantially 90-degree angle (see Fig.9b where 8 has two features making a corner). Regarding claim 15, Nakamura discloses wherein the at least two downset features comprise corners with rounded shape (see rounded corner 8 in Fig.9e). Regarding claim 16, Nakamura discloses wherein the at least two downset features comprise corners with rounded edge (see rounded corner 8 in Fig.9e). Regarding claim 17, Nakamura discloses wherein the at least two downset features comprising a mold lock pattern formed therein (see male-female locking pattern between 3 and 8;Fig.5). Allowable Subject Matter Claim 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner's statement of reasons for allowance: Regarding claim 9, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the mold lock pattern is a dimpled pattern " in combination with the remaining limitations of the claim 1. Therefore, prior art of record neither anticipates nor renders obvious the instantapplication claimed invention as a whole either taken alone or in combination. Any comments considered necessary by applicant must be submitted no laterthan the payment of the issue fee and, to avoid processing delays, should preferablyaccompany the issue fee. Such submissions should be clearly labeled "Comments onStatement of Reasons for Allowance." Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /PETE T LEE/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

May 15, 2024
Application Filed
Feb 07, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
85%
With Interview (+10.5%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 773 resolved cases by this examiner. Grant probability derived from career allow rate.

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