Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the application 18/664,589 filed on 05/15/2024.
Claims 1-20 have been examined and are pending in this application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-19 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 11, claim 11 recite “a processor; and a memory coupled to the processor, wherein the processor is configured to:” it is unclear, how a processor coupled with memory execute all the required steps such as: determine…., reading…., verifying…. and allowing…… etc. It is not clear that the processor is actually executing any stored instructions to determine, determine, read, verify and allow or not.
Regarding claims 12-19; claims 12-19 are dependent on claim 11, and are analyzed and rejected accordingly.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being unpatentable over Montero (US 2024/0168910).
Regarding claim 1, Montero discloses a method of operation of a baseboard management controller (BMC) (Montero abstract and par. 0049; Systems and methods for loading firmware onto an embedded controller (EC) integrated into a heterogenous computing platform. EC 109 (sometimes referred to as a Baseboard Management Controller or “BMC”) handles certain IHS operations not ordinarily handled by host processor(s) 101), comprising:
determining to reboot a hardware component, wherein a firmware image for the hardware component is stored in a non-volatile memory of the hardware component (Montero par. 0053-0054 par. 0060; EC 109 calculate a hash value based on the configuration of a hardware and/or software component coupled to IHS 100. For instance, EC 109 may calculate a hash value based on all firmware and other code or settings stored in an onboard memory of a hardware component. EC 109 validate the integrity of hardware and software components installed in IHS 100. In some implementations, the latest system-wide firmware installation package received by platform 200 may be installed at every boot of IHS 100);
reading, by the BMC, the firmware image of the hardware component from the non- volatile memory of the hardware component (Montero par. 0122; EC 109A/B receives EC firmware instructions, configuration settings, or tables 706A-N from PCIe devices 705A-N. At 804, EC 109A/B cryptographically verifies the integrity or authenticity of EC firmware instructions, configuration settings, or tables 706A-N. For example, each of PCIe devices 705A-N may be provisioned with its own digital certificate);
verifying, by the BMC using a public key of a public-private key pair, the firmware image of the hardware component to determine integrity and authenticity of the firmware image, wherein the public key is stored in a BMC firmware image (Montero par. 0115; EC 109A/B may validate the PCIe-acquired EC firmware via using asymmetric cryptography (e.g., Elliptic Curve Cryptography or “ECC”), such that the firmware is signed with a private key on the build server and verified by IHS 100 with a matching public key on EC 109A/B (e.g., stored in its boot ROM firmware). See also claim 19, par. 0049 and 0123); and
allowing, by the BMC, the hardware component to boot from the firmware image in response to the firmware image passing the verification (Montero par. 0125; At 805, in response to a successful validation, verification, or authentication, EC 109A/B stores EC firmware instructions, configuration settings, or tables 706A-N in EC RAM 701 to be used during the current boot of IHS 100, in the next boot of IHS 100, and/or as part of rebootless firmware updates. Otherwise, EC 109A/B may reject EC firmware instructions, configuration settings, or tables 706A-N).
Regarding claim 2, Montero disclose the method of claim 1,
Montero further discloses further comprising: preventing, by the BMC, the hardware component from booting from the firmware image in response to the firmware image failing the verification (Montero par. 0125; At 805, in response to a successful validation, verification, or authentication, EC 109A/B stores EC firmware instructions, configuration settings, or tables 706A-N in EC RAM 701 to be used during the current boot of IHS 100, in the next boot of IHS 100, and/or as part of rebootless firmware updates).
Regarding claim 3, Montero disclose the method of claim 1,
Montero further discloses wherein the verifying the firmware image comprises: calculating a hash value of the firmware image; inputting the hash value and a digital signature stored with the firmware image into a signature verification algorithm; and receiving an output of the signature verification algorithm that indicates validity of the digital signature (Montero par. 0053-0054 and 0060; EC 109 calculate a hash value based on the configuration of a hardware and/or software component coupled to IHS 100. For instance, EC 109 may calculate a hash value based on all firmware and other code or settings stored in an onboard memory of a hardware component).
Regarding claim 4, Montero disclose the method of claim 3,
Montero further discloses wherein the digital signature comprises an Elliptic Curve Digital Signature Algorithm (ECDSA) signature generated by signing the hash value using a private key of the public-private key pair (Montero par. 0115; EC 109A/B may validate the PCIe-acquired EC firmware via using asymmetric cryptography (e.g., Elliptic Curve Cryptography or “ECC”), such that the firmware is signed with a private key on the build server and verified by IHS 100 with a matching public key on EC 109A/B (e.g., stored in its boot ROM firmware)).
Regarding claim 5, Montero disclose the method of claim 1,
Montero further discloses wherein the verifying the firmware image comprises: verifying integrity of a manifest table within the firmware image by calculating a hash of the manifest table and comparing the calculated hash to a stored hash value in the firmware image (Montero par. 0053-0054 and 0060; EC 109 calculate a hash value based on the configuration of a hardware and/or software component coupled to IHS 100. For instance, EC 109 may calculate a hash value based on all firmware and other code or settings stored in an onboard memory of a hardware component).
Regarding claim 6, Montero disclose the method of claim 1,
Montero further discloses wherein allowing the hardware component to boot from the firmware image comprises: allowing the hardware component to load the firmware image from the non-volatile memory into a volatile memory of the hardware component and execute the firmware image (Montero par. 0114; Other PCIe access models may load the EC firmware image from a trusted network connection and/or from the cloud or Internet. As such, new PCIe connectivity and resources can provide alternatives to the otherwise conventional process of loading EC firmware from a flash device (e.g., SPI flash).).
Regarding claim 7, Montero disclose the method of claim 1,
Montero further discloses wherein the hardware component is one of: a network interface card (NIC), a redundant array of independent disks (RAID) controller, a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a graphics processing unit (GPU), or a Peripheral Component Interconnect Express (PCIe) switch (Montero abstract; A heterogeneous computing platform having a Reduced Instruction Set Computer (RISC) processor and a Peripheral Component Interconnect Express (PCIe) controller coupled thereto).
Regarding claim 8, Montero disclose the method of claim 1,
Montero further discloses wherein the BMC controls power sequencing of the hardware component, the method further comprising: powering on the hardware component by the BMC after that the firmware image passes the verification (Montero par. 0111; In response to a power-on or reset event. As a result, EC 109A/B (as well as devices 401L-N) may be operational before host processor(s) 101, devices 401A-K, and/or host OS 300 are up and running).
Regarding claim 9, Montero disclose the method of claim 1,
Montero further discloses wherein the public key comprises an Elliptic Curve (EC) public key, and wherein the BMC firmware image stores X and Y components representing coordinates of the public key on an elliptic curve (Montero par. 0115; EC 109A/B may validate the PCIe-acquired EC firmware via using asymmetric cryptography (e.g., Elliptic Curve Cryptography or “ECC”)).
Regarding claim 10, Montero disclose the method of claim 1,
Montero further discloses wherein the verifying the firmware image comprises: verifying an initial boot block (IBB) of the firmware image using the public key, wherein the IBB comprises a first section of the firmware image; and allowing the hardware component to load and execute the IBB to verify remaining sections of the firmware image (Montero par. 0115; EC 109A/B (e.g., stored in its boot ROM firmware). Validating the EC firmware cryptographically before running it, as the very first device in platform 200A/B to run at the system level, alleviates potential security problems and enables EC 109A/B to act as the root of trust for IHS 100).
Regarding claims 11-19; claims 11-19 are directed to a controller associated with the method claimed in claims 1-9 respectively. Claims 11-19 are similar in scope to claims 1-9 respectively, and are therefore rejected under similar rationale.
Regarding claim 20; claim 20 is directed to a non-transitory computer readable medium associated with the method claimed in claim 1. Claim 20 is similar in scope to claim 1, and is therefore rejected under similar rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANCHIT K SARKER whose telephone number is (571)270-7907. The examiner can normally be reached M-F 8:30 AM-5:30 PM.
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/SANCHIT K SARKER/Primary Examiner, Art Unit 2495