DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to a claim of priority to Japanese application JP2023-085165 filed on May 24th, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) filed on May 15th, 2024 and March 6th, 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is being considered by the examiner.
Specification
The following guidelines illustrate the preferred layout for the specification of a utility application. These guidelines are suggested for the applicant’s use.
Arrangement of the Specification
As provided in 37 CFR 1.77(b), the specification of a utility application should include the following sections in order. Each of the lettered items should appear in upper case, without underlining or bold type, as a section heading. If no text follows the section heading, the phrase “Not Applicable” should follow the section heading:
(a) TITLE OF THE INVENTION.
(b) CROSS-REFERENCE TO RELATED APPLICATIONS.
(c) STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT.
(d) THE NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT.
(e) INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A READ-ONLY OPTICAL DISC, AS A TEXT FILE OR AN XML FILE VIA THE PATENT ELECTRONIC SYSTEM.
(f) STATEMENT REGARDING PRIOR DISCLOSURES BY THE INVENTOR OR A JOINT INVENTOR.
(g) BACKGROUND OF THE INVENTION.
(1) Field of the Invention.
(2) Description of Related Art including information disclosed under 37 CFR 1.97 and 1.98.
(h) BRIEF SUMMARY OF THE INVENTION.
(i) BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S).
(j) DETAILED DESCRIPTION OF THE INVENTION.
(k) CLAIM OR CLAIMS (commencing on a separate sheet).
(l) ABSTRACT OF THE DISCLOSURE (commencing on a separate sheet).
(m) SEQUENCE LISTING. (See MPEP § 2422.03 and 37 CFR 1.821 - 1.825). A “Sequence Listing” is required on paper if the application discloses a nucleotide or amino acid sequence as defined in 37 CFR 1.821(a) and if the required “Sequence Listing” is not submitted as an electronic document either on read-only optical disc or as a text file via the patent electronic system.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Sekiya (US20210134619A1) in view of Harada et al. (US20200388537A1) for the following reasons:
Regarding claim 1;
Sekiya teaches a wafer processing method (e.g. Fig. 3-4, Fig. 5-18) for processing a wafer (e.g. ref 10, detailed description [0033] “…wafer 10 refers to a wafer such as a semiconductor wafer or an optical device wafer that is shaped as a circular plate…”) including a reverse side (e.g. ref 19, detailed description [0034] “… the reverse side 19 of the wafer 10 is positioned opposite the face side 12 where the devices 14 are formed.”) which has an annular protruding portion on an outer circumferential portion (e.g. ref 16) thereof and a circular recessed portion (e.g. ref 20, summary of invention [0006] “…the wafer further including a circular recess defined by grinding in a reverse side of the wafer and corresponding to the device region…”) in a region surrounded by the annular protruding portion, the wafer processing method comprising: a wafer unit forming step of forming a wafer unit by fixing a sheet including a glue layer (e.g. detailed description [0043] “The protective member 31 includes a base layer made of an elastic synthetic resin and a glue layer made of an elastic and adhesive synthetic resin and layered on at least either one of face and reverse sides of the base layer.”) to a face side of the wafer and fixing an annular frame to an outer circumferential portion of the sheet (e.g. ref ST3, detailed description [0041] “The protective member affixing step ST3 is a step of affixing a protective member 31 whose area covers the face side 12 or the reverse side 19 of the wafer 10 to the wafer 10. According to the present embodiment, in the protective member affixing step ST3, an outer circumferential edge of the protective member 31 that covers the face side 12 or the reverse side 19 of the wafer 10 is affixed to an annular frame 32, forming a frame unit 1 or 1-2 in which the wafer 10 is supported on the protective member 31 in an opening of the annular frame 32.”); a holding step of holding the wafer on a holding table (e.g. ref 65) via the sheet (e.g. see examiner markup, detailed description [0055] “…the face side 12 of the wafer 10 is held under suction on the holding surface 56 of the chuck table 55 with the protective member 31 interposed between the face side 12 and the holding surface 56. At this time, the annular frame 32 that is pressed downwardly below the face side 12 of the wafer 10 is secured in place by clamps or the like, not illustrated, fixing the face side 12 of the wafer 10 to the holding surface 56 of the chuck table 55.”), after the wafer unit forming step; a dividing step of forming a dividing groove in the circular recessed portion of the wafer and separating the annular protruding portion from the wafer (e.g. ref ST41, detailed description [0055] “…the ring-shaped stiffener separating step ST41, the cutting unit 50 separates the device region 15 and the ring-shaped stiffener 21 from each other…”), after the holding step; and a removing step of removing the annular protruding portion from the sheet, after the dividing step (e.g. ref ST42, detailed description [0074] “…the cutting unit 70 grinds off the ring-shaped stiffener 21 that has been separated from the device region 15…”).
Sekiya is silent to the omission of a glue layer from the sheet as claimed.
However, Harada et al. teaches an analogous method of processing a wafer which includes fixing a sheet including no glue layer (e.g. ref 9, detailed description [0035] “The polyester sheet 9 is a flexible (expandable) resin sheet, and it has a flat front side and a flat back side. The polyester sheet 9 is a circular sheet having a diameter larger than the outer diameter of the ring frame 7. The polyester sheet 9 has no adhesive layer.”) to a face side of the wafer (e.g. detailed description [0038] “After the wafer 1 and the frame 7 are placed on the holding surface 2 a of the chuck table 2, the polyester sheet 9 is provided on the back side 1 b (or the front side 1 a) (upper surface) of the wafer 1 and on the back side 7 c (upper surface) of the ring frame 7”).
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to modify the method taught in Sekiya to include the processing step taught in Harada et al. which includes a sheet with no glue layer because the omission of an adhesive layer from the boding of the sheet and wafer would prevent the devices resulting from the method from being damaged due to adhesive residues (e.g. summary of invention [0005]-[0006]) as well as produce a more streamlined method by not requiring an additional step of removing the adhesive sheet.
Regarding claim 2;
Sekiya is silent to wafer unit forming step fixing the sheet to the wafer by being heated, pressed against, and thermocompression-bonded to the wafer as claimed.
However, Harada et al. teaches explicitly teaches that the sheet and (e.g. Detailed description [0035] “Since the polyester sheet 9 has no adhesive property, it cannot be attached to the wafer 1 and the ring frame 7 at room temperature. However, the polyester sheet 9 is a thermoplastic sheet, so that, when the polyester sheet 9 is heated to a temperature near its melting point under a predetermined pressure in a condition where the polyester sheet 9 is in contact with the wafer 1 and the ring frame 7, the polyester sheet 9 is partially melted and thereby bonded to the wafer 1 and the ring frame 7. That is, by applying heat and pressure to the polyester sheet 9 in the condition where the polyester sheet 9 is in contact with the wafer 1 and the ring frame 7, the polyester sheet 9 can be bonded to the wafer 1 and the ring frame 7. Thusly, in the processing method for the wafer 1 according to this preferred embodiment, all of the wafer 1, the ring frame 7, and the polyester sheet 9 are united by thermocompression bonding as mentioned above, thereby forming the frame unit.”).
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to modify the method taught in Sekiya to include the thermocompression bonding step taught in Harada et al. as a substitute to the originally taught wafer-sheet bonding step to improve the interface adhesion between wafer and protective sheet in the absence of an adhesive agent because thermocompression bonding is a process known in the art to improve bonding between adjacent material layers via solid-state bonding mechanisms (e.g. diffusion bonding) predictably improving the mechanical integrity of the resulting bond, and further improving the resulting device quality by avoiding melting of the sheet due to excessive temperatures (e.g. detailed description [0047]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kajiyama et al. (US7718511B2) teaches a wafer processing method which includes a step of holding an intermediate product on a holding table.
Priewasser (US20080248730A1) teaches a wafer processing method including a step of removing an outer circumferential reinforcing portion.
Sekiya (US7348275B2) teaches a processing method for a semiconductor wafer which is generally circular and has an annular surplus region.
Sekiya (CN114613726A) teaches a wafer processing method which includes attaching a protecting sheet with an adhesive layer to a front side of the wafer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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