Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The status of the claims is as follows:
Claims 1-20 are pending.
An action on the merits for claims 1-20 follows.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)
(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
IDS
All references provided in the IDS have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Semiconductor Device Having Multiple Bit Line Spacers.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-9, 11-13, 15-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20200194439 A1), hereinafter Kim.
Regarding Claim 1, Kim teaches a semiconductor device ("semiconductor device;" Figs. 1 (schematic view), 2 (partial perspective view), 3, (cross-sectional view taken along portion of line A-A' of Fig. 1), 4A (enlarged view of Fig. 4), Paragraph [0017]; Note: Fig. 4A principally shows and labels the necessary elements except for those not visible on the plane of its cross-section), comprising:
a substrate ("substrate," (1); Fig. 2, Paragraph [0018]);
an active region ("active regions," (AR); Fig. 1, Paragraph [0019]) defined by a device isolation layer ("device isolation layer," (3); Figs. 3, 4A, Paragraph [0018]) within the substrate (1);
a word line ("word line," (WL); Fig. 2, Paragraph [0018]) extending in a first horizontal direction (D2; Fig. 2, Paragraph [0020]) within the substrate (1), the first horizontal direction (D2) parallel to an upper surface of the substrate (1);
a bit line ("bit line," (BL); Figs. 2, 4A, Paragraph [0024]) extending on the substrate (1) in a second horizontal direction (D3; Fig. 2, Paragraph [0024]) parallel to the upper surface of the substrate (1) and intersecting with the first horizontal direction (D2), the bit line (BL) including a metal-based conductive pattern ("second bit line," (BLb); Fig. 4A, Paragraph [0033]);
a first spacer ("first bit line spacer," (23); Fig. 4A, Paragraph [0042]) on a sidewall of the metal-based conductive pattern (BLb);
a second spacer ("second bit line spacer," (26); Paragraph [0042]) on the first spacer (23);
a direct contact ("bit line node contact," (DC); Fig. 4A, Paragraph [0032]) in a direct contact hole ("direct contact hole," (DH); Annotated Fig. 4A) exposing the active region (AR), the direct contact (DC) electrically connecting (Paragraph [0024]) the bit line (BL) to the active region (AR); and
a buried spacer ("lower spacer," (SS1); Fig. 4A, Paragraph [0036]) on a lower portion of a sidewall of the direct contact (DC) within the direct contact hole (DH),
wherein the second spacer (26) contacts the sidewall of the direct contact (DC). (The term “contact” is understood to permit intervening elements in the same plane between two “contacting elements” in line with the present specification Paragraph [0022].)
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Regarding Claim 4, Kim teaches the semiconductor device (Figs. 1-4A) of claim 1, wherein the sidewall of the direct contact (DC) includes at least a portion that is not in contact with the first spacer (23, (Fig. 4A)).
Regarding Claim 5, Kim teaches the semiconductor device (Figs. 1-4A) of claim 1, wherein the first spacer (23) includes a nitride ("23 may include silicon nitride;" Paragraph [0043]), and the second spacer (26) includes an oxide ("26 may include silicon oxide;" Paragraph [0045]).
Regarding Claim 6, Kim teaches the semiconductor device (Figs. 1-4A) of claim 5, wherein the first spacer (23) includes one or more materials selected from silicon boron nitride, silicon carbon nitride, silicon oxide nitride, and silicon carbon oxynitride (“the spacer SS may be formed of […] silicon oxynitride;” Paragraph [0025]; 23 is a component of SS and therefore may comprise silicon oxynitride).
Regarding Claim 7, Kim teaches the semiconductor device (Figs. 1-4A) of claim 1,
wherein the buried spacer (SS1) comprises:
an insulating liner (“first contact spacer,” (10); Fig. 4A, Paragraph [0037]) on an inner wall of the direct contact hole (DH) and the lower portion of the sidewall of the direct contact (DC); and
a buried insulating layer (“second contact spacer,” (20); Paragraph [0037]) at least partially filling the direct contact hole (DH) on the insulating liner (10).
Regarding Claim 8, Kim teaches the semiconductor device (Figs. 1-4) of claim 7, wherein the insulating liner (10) is in contact with the lower portion of the sidewall of the direct contact (DC, Fig. 4A).
Regarding Claim 9, Kim teaches the semiconductor device (Figs. 1-4) of claim 7, wherein the insulating liner (10) includes an oxide (“10 may include silicon oxide;” Paragraph [0037]), and the buried insulating layer (20) includes a nitride (“20 may include silicon nitride;” Paragraph [0037]).
Regarding Claim 11, Kim teaches a semiconductor device ("semiconductor device;" Figs. 1 (schematic view), 2 (partial perspective view), 3, (cross-sectional view taken along portion of line A-A' of Fig. 1), 4A (enlarged view of Fig. 4), Paragraph [0017]; Note: Fig. 4A principally shows and labels the necessary elements except for those not visible on the plane of its cross-section), comprising:
a substrate ("substrate," (1); Fig. 2, Paragraph [0018]);
an active region ("active regions," (AR); Fig. 1, Paragraph [0019]) defined by a device isolation layer ("device isolation layer," (3); Figs. 3, 4A, Paragraph [0018]) within the substrate (1);
a word line ("word line," (WL); Fig. 2, Paragraph [0018]) crossing the active region (AR) in a first horizontal direction (D2; Fig. 2, Paragraph [0020]) parallel to an upper surface of the substrate (1), the word line (WR) dividing the active region (AR) into a first impurity region ("second impurity implantation region," (6d); Figs. 2, 3, Paragraph [0021]) and a second impurity region ("first impurity implantation region," (6s); Figs. 2, 3, Paragraph [0021]);
a bit line ("bit line," (BL); Figs. 2, 4A, Paragraph [0024]) extending in a second horizontal direction (D3; Fig. 2, Paragraph [0024]) parallel to the upper surface of the substrate (1) and intersecting with the first horizontal direction (D2) on the substrate (1), the bit line (BL) including a conductive semiconductor pattern ("first bit line," (BLa); Fig. 4A, Paragraph [0034]) and a metal-based conductive pattern ("second bit line," (BLb); Fig. 4A, Paragraph [0033]) that are sequentially stacked;
a first spacer ("first bit line spacer," (23); Fig. 4A, Paragraph [0042]) on a sidewall of the metal-based conductive pattern (BLb);
a second spacer ("second bit line spacer," (26); Paragraph [0042]) on the first spacer (23);
a direct contact ("bit line node contact," (DC); Fig. 4A, Paragraph [0032]) in a direct contact hole ("direct contact hole," (DH); Annotated Fig. 4A) at least partially exposing the first impurity region (6d), the direct contact (DC) electrically connecting (Paragraph [0024]) the bit line (BL) to the first impurity region (6d);
a buried contact ("storage node contact," (BC); Figs. 3, 4, Paragraph [0035]) in a buried contact hole ("storage node contact hole," (BH); Paragraph [0035]) at least partially exposing the second impurity region (6s), wherein the buried contact (BC) is electrically connected (Paragraph [0031]) to the second impurity region (6s) on a sidewall of the bit line (BL); and
a buried spacer ("lower spacer," (SS1); Fig. 4A, Paragraph [0036]) on a lower portion of a sidewall of the direct contact (DC) within the direct contact hole (DH),
wherein the second spacer (26) contacts a sidewall of the conductive semiconductor pattern (BLa).
Regarding Claim 12, Kim teaches the semiconductor device (Figs. 1-4A) of claim 11, wherein the second spacer (26) is in contact with an upper portion of the sidewall of the direct contact (DC).
Regarding Claim 13, Kim teaches the semiconductor device (Figs. 1-4A) of claim 12, wherein the sidewall of the direct contact (DC) includes at least a portion that is not in contact with the first spacer (23; Fig. 4A).
Regarding Claim 15, Kim teaches the semiconductor device (Figs. 1-4A) of claim 11, wherein the first spacer (23) includes a nitride ("23 may include silicon nitride;" Paragraph [0043]), and the second spacer (26) includes an oxide ("26 may include silicon oxide;" Paragraph [0045]).
Regarding Claim 16, Kim teaches the semiconductor device (Figs. 1-4A) of claim 11,
wherein the buried spacer (SS1) comprises:
an insulating liner (“first contact spacer,” (10); Fig. 4A, Paragraph [0037]) on an inner wall of the direct contact hole (DH) and the lower portion of the sidewall of the direct contact (DC); and
a buried insulating layer (“second contact spacer,” (20); Paragraph [0037]) at least partially filling the direct contact hole (DH) on the insulating liner (10).
Regarding Claim 17, Kim teaches the semiconductor device (Figs. 1-4A) of claim 16, wherein the insulating liner (10) includes an oxide (“10 may include silicon oxide;” Paragraph [0037]), and the buried insulating layer (20) includes a nitride (“20 may include silicon nitride;” Paragraph [0037]).
Regarding Claim 18, Kim teaches a semiconductor device ("semiconductor device;" Figs. 1 (schematic view), 2 (partial perspective view), 3, (cross-sectional view taken along portion of line A-A' of Fig. 1), 4A (enlarged view of Fig. 4), Paragraph [0017]; Note: Fig. 4A principally shows and labels the necessary elements except for those not visible on the plane of its cross-section), comprising:
a substrate ("substrate," (1); Fig. 2, Paragraph [0018]);
a device isolation layer ("device isolation layer," (3); Figs. 3, 4A, Paragraph [0018]) defining an active region ("active regions," (AR); Fig. 1, Paragraph [0019]) within the substrate (1), the active region (AR) including a first impurity region ("second impurity implantation region," (6d); Figs. 2, 3, Paragraph [0021]) and second impurity regions (("first impurity implantation region," (6s); Figs. 2, 3, Paragraph [0021])), the second impurity regions (6s) spaced apart from each other with the first impurity region (6d) therebetween (Fig. 3);
a word line ("word line," (WL); Fig. 2, Paragraph [0018]) crossing between the first impurity region (6d) and the second impurity regions (6s) and extending in a first horizontal direction (D2; Fig. 2, Paragraph [0020]) within the substrate (1), the first horizontal direction (D2) parallel to an upper surface of the substrate (1);
a bit line ("bit line," (BL); Figs. 2, 4A, Paragraph [0024]) extending on the substrate (1) in a second horizontal direction (D3; Fig. 2, Paragraph [0024]), the second horizontal direction (D3) parallel to the upper surface of the substrate (1) and intersecting with the first horizontal direction (D2), the bit line (BL) including a conductive semiconductor pattern ("first bit line," (BLa); Fig. 4A, Paragraph [0034]) and a metal-based conductive pattern ("second bit line," (BLb); Fig. 4A, Paragraph [0033]) that are sequentially stacked;
a first spacer ("first bit line spacer," (23); Fig. 4A, Paragraph [0042]) on a sidewall of the metal-based conductive pattern (BLb); and including a nitride ("23 may include silicon nitride;" Paragraph [0043]);
a second spacer ("second bit line spacer," (26); Paragraph [0042]) on the first spacer (23) and a sidewall of the conductive semiconductor pattern (BLa) and including an oxide ("26 may include silicon oxide;" Paragraph [0045]);
a direct contact ("bit line node contact," (DC); Fig. 4A, Paragraph [0032]) in a direct contact hole ("direct contact hole," (DH); Annotated Fig. 4A) exposing the first impurity region (6d), the direct contact (DC) electrically connecting (Paragraph [0024]) the bit line (BL) to the first impurity region (6d);
a buried contact ("storage node contact," (BC); Figs. 3, 4, Paragraph [0035]) in a buried contact hole ("storage node contact hole," (BH); Paragraph [0035]) exposing the second impurity region (6s), wherein the buried contact (BC) is electrically connected (Paragraph [0031]) to the second impurity region (6s) on a sidewall of the bit line (BL); and
a buried spacer ("lower spacer," (SS1); Fig. 4A, Paragraph [0036]) on a lower sidewall of the direct contact (DC) within the direct contact hole (DH),
wherein the second spacer (26) contacts a sidewall of the direct contact (DC) on the sidewall of the direct contact (DC), and contacts the sidewall of the conductive semiconductor pattern (BLa) on the sidewall of the conductive semiconductor pattern (BLa).
Regarding Claim 20, Kim teaches the semiconductor device (Figs. 1-4A) of claim 18, wherein the buried spacer (SS1) comprises:
an insulating liner (“first contact spacer,” (10); Fig. 4A, Paragraph [0037]) on an inner wall of the direct contact hole (DH) and the lower portion of the sidewall of the direct contact (DC), and comprising an oxide (“10 may include silicon oxide;” Paragraph [0037]); and
a buried insulating layer (“second contact spacer,” (20); Paragraph [0037]) at least partially filling the direct contact hole (DH) on the insulating liner (10) and includes a nitride
(“20 may include silicon nitride;” Paragraph [0037]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 14, and, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee et al. (KR 20220082507 A), hereinafter Lee. (Note: the attached English machine translation is used for citation purposes herein.)
Regarding Claim 2, Kim teaches the semiconductor device (Figs. 1-4A) of claim 1,
wherein the bit line (BL) further includes a conductive semiconductor pattern (("first bit line," (BLa); Fig. 4A, Paragraph [0034])) between the metal-based conductive pattern (BLb) and the substrate (1).
Kim does not explicitly teach wherein a sidewall of the conductive semiconductor pattern includes at least a portion that is not in contact with the first spacer.
Lee teaches a semiconductor device (“semiconductor device;” Fig. 2, Paragraph [0012]) wherein a sidewall of the conductive semiconductor pattern (“first conductive pattern,” (245); Paragraph [0020]) includes at least a portion that is not in contact with the first spacer (“first upper spacer,” (305); Fig. 2, Paragraph [0030]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device of Kim with the teachings of Lee such that the conductive semiconductor pattern includes at least a portion that is not in contact with the first spacer. The nitrogen containing first spacer being only located on the upper sidewall of the bit line, leaving space for an oxide second spacer to contact the lower part of the bit line including a conductive semiconductor pattern, prevents trapping of electrons (Paragraph [0048]) and deterioration of resistance (Paragraph [0050]). This has the added benefit of allowing current to flow smoothly through the bit line (Paragraph [0051]).
Regarding Claim 3, Kim as modified by Lee teaches the semiconductor device (Kim, Figs. 1-4A) of claim 2, wherein the second spacer (26) is in contact with the sidewall of the conductive semiconductor pattern (BLa).
Regarding Claim 14, Kim teaches the semiconductor device (Figs. 1-4A) of claim 11.
Kim does not explicitly teach wherein the sidewall of the conductive semiconductor pattern includes at least a portion that is not in contact with the first spacer.
Lee teaches a semiconductor device (“semiconductor device;” Fig. 2, Paragraph [0012]) wherein the sidewall of the conductive semiconductor pattern (“first conductive pattern,” (245); Paragraph [0020]) includes at least a portion that is not in contact with the first spacer (“first upper spacer,” (305); Fig. 2, Paragraph [0030]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device of Kim with the teachings of Lee such that the conductive semiconductor pattern includes at least a portion that is not in contact with the first spacer. The nitrogen containing first spacer being only located on the upper sidewall of the bit line, leaving space for an oxide second spacer to contact the lower part of the bit line including a conductive semiconductor pattern, prevents trapping of electrons (Paragraph [0048]) and deterioration of resistance (Paragraph [0050]). This has the added benefit of allowing current to flow smoothly through the bit line (Paragraph [0051]).
Regarding Claim 19, Kim teaches the semiconductor device (Figs. 1-4A) of claim 18,
Wherein the sidewall of the direct contact (DC) includes at least a portion that is not in contact with the first spacer (23, (Fig. 4A)).
Kim does not explicitly teach wherein the sidewall of the conductive semiconductor pattern includes at least a portion that is not in contact with the first spacer.
Lee teaches a semiconductor device (“semiconductor device;” Fig. 2, Paragraph [0012]) wherein the sidewall of the conductive semiconductor pattern (“first conductive pattern,” (245); Paragraph [0020]) includes at least a portion that is not in contact with the first spacer (“first upper spacer,” (305); Fig. 2, Paragraph [0030]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device of Kim with the teachings of Lee such that the conductive semiconductor pattern includes at least a portion that is not in contact with the first spacer. The nitrogen containing first spacer being only located on the upper sidewall of the bit line, leaving space for an oxide second spacer to contact the lower part of the bit line including a conductive semiconductor pattern, prevents trapping of electrons (Paragraph [0048]) and deterioration of resistance (Paragraph [0050]). This has the added benefit of allowing current to flow smoothly through the bit line (Paragraph [0051]).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Sung (US 20230017800 A1), hereinafter Sung.
Regarding Claim 10, Kim teaches the semiconductor device (Figs. 1-4A) of claim 1.
Kim does not explicitly teach wherein a thickness of the first spacer in the first horizontal direction is about 0.3 nm to about 1 nm.
Sung teaches a semiconductor device (“semiconductor device,” (100); Figs. 1 (plan-view) 2A (cross-section along 2B), Paragraph [0023]) wherein a thickness of the first spacer (“first spacer,” (215); Fig. 2A, Paragraph [0028]) in the first horizontal direction (second direction,” (2D); Fig. 1, Paragraph [0027]) is about 0.3 nm to about 1 nm (“approximately 10 Å or less;” Paragraph [0028]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device of Kim with the teachings of Sung such that the thickness of the first spacer in the first horizontal direction is about 0.3 nm to about 1 nm. This is because having a low thickness had the benefit of suppressing an increase in parasitic capacitance (Paragraph [0039]).
Conclusion
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/NOLAN GABRIEL STUESSY/ Examiner, Art Unit 2812
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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