Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I in the reply filed on 7/30/2026 is acknowledged. The traversal is on the ground(s) that the examiner has. This is not found persuasive because Invention I requires searching for prior art of processes of manufacture, while invention II requires search for prior art of a device. These two, while they may have similar limitations, require completely different prior art searches due to their individual scopes. The inventions, while each having similar limitations on the micro-scale, are, on a macro-scale, fundamentally distinct.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6-9, and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 20210328020 A1), in view of Cheng (US 20210210598 A1).
Regarding independent claim 1, Chung teaches a method for forming a source-drain for a stacked nanosheet structure ([0014], "Method 100 is described below in conjunction with FIG. 2A-16A, 2B-10B, and 12B-14B, which are fragmentary cross-sectional views of the semiconductor device at different stages of fabrication according to embodiments of the method 100 in FIG. 1.", [0003], "The channel region of an MBC transistor may be formed from nanowires, nanosheets, other nanostructures, and/or other suitable structures."), comprising: stopping the epitaxial growth process prior to a crystal structure of one of the plurality of epitaxial growth layers on one channel of the stacked nanosheet structure merging into another crystal structure of any other one of the plurality of epitaxial growth layers on another channel of the stacked nanosheet structure or merging into surfaces of the inner spacers ([0028], "In some alternative embodiments represented in FIGS. 12A and 12B, a second outer epitaxial feature 230, rather than the first outer epitaxial feature 228, are epitaxially grown from the exposed channel layers 208 and the substrate 202 but do not coalesce to merge over the inner spacer features 226."); and forming a compressive stress material on the plurality of epitaxial growth layers (Fig. 15A, 234, 230; [0031], "In some alternative embodiments represented in FIGS. 13A and 13B, when the second outer epitaxial feature 230 is implemented at block 114, block 116 of method 100 may deposit a second inner epitaxial feature 234 over the second outer epitaxial feature 230.", [0013], "In other embodiments, the germanium (Ge) in the outer epitaxial layer or the inner epitaxial layer may be replaced with germanium tin (GeSn) to introduce compressive stress.").
However, Chung does not teach forming an epitaxial growth layer on each of a plurality of channels of the stacked nanosheet structure using an epitaxial growth process to form a plurality of epitaxial growth layers, wherein a material of the plurality of channels is a silicon-based material and wherein the plurality of channels are separated by inner spacers of a dielectric material.
However, in the same field of endeavor, Cheng teaches forming an epitaxial growth layer on each of a plurality of channels of the stacked nanosheet structure using an epitaxial growth process to form a plurality of epitaxial growth layers (Fig. 8, 122; [0044], "In one illustrative embodiment, the isolation layer 122 comprises silicon (Si) which is epitaxially grown via conventional methodologies such as vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), etc., within the gaps 120 and within the channel recesses 118 of the channel nanosheets 108."), wherein a material of the plurality of channels is a silicon-based material and wherein the plurality of channels are separated by inner spacers of a dielectric material (Fig. 13, 108, 128; [0033], "...the channel nanosheets 108 comprise silicon (Si).", [0051], "Referring now to FIG. 13, the process is continued by forming a high-k/metal gate 128 around the channel nanosheets 108 and within the void left by removal of the dummy gate 110. For example, a high-k dielectric material can be deposited to form a gate dielectric.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of Chung with the silicon channels of Cheng for "increasing the effective channel width of the resulting device", (Cheng, [0001]).
Regarding dependent claim 2, Chung, as previously modified by Cheng, teaches the method of claim 1, and further teaches wherein the compressive stress material fills a remaining portion of a source-drain cavity (Fig. 15A, 234; [0031], "The second outer epitaxial feature 230 and the second inner epitaxial feature 234 may be regarded collectively as a second source/drain feature 2320 that is disposed over the source/drain regions 210SD.").
Regarding dependent claim 3, Chung, as previously modified by Cheng, teaches the method of claim 2, and further teaches wherein the compressive stress material is a selectively formed tin germanium (SnGe) epitaxial material ([0029], "In some embodiments, the first inner epitaxial feature 232 may be epitaxially and selectively formed from the first outer epitaxial feature 228.", [0029], "In other instances, the first inner epitaxial feature 232 includes germanium tin (GeSn) doped with the second p-type dopant.", [0031], "As shown in FIGS. 9A and 13A, one of the differences between the first inner filler 232 and the second inner filler 234 lies in that the second inner filler 234 is allowed to come in contact with the inner spacer features 226 but the first inner filler 232 is not.', (232 and 234 are the same feature but in different embodiments)).
Regarding dependent claim 6, Chung, as previously modified by Cheng, teaches the method of claim 1, and further teaches wherein the compressive stress material is a layer on each of the plurality of epitaxial growth layers (Fig. 15A, 234, 230; [0031], "In some alternative embodiments represented in FIGS. 13A and 13B, when the second outer epitaxial feature 230 is implemented at block 114, block 116 of method 100 may deposit a second inner epitaxial feature 234 over the second outer epitaxial feature 230.", (It is on each of the epitaxial growth layers)).
Regrading dependent claim 7, Chung, as previously modified by Cheng, teaches the method of claim 6, and further teaches wherein the layer of the compressive stress material has a thickness of greater than zero to approximately 3nm ([0029], "In some embodiments, the first inner epitaxial feature 232 may have a thickness between about 1 nm and about 6 nm…").
Regarding dependent claim 8, Chung, as previously modified by Cheng, teaches the method of claim 6, and further teaches wherein the compressive stress material is selectively formed on the plurality of epitaxial growth layers ([0029], "In some embodiments, the first inner epitaxial feature 232 may be epitaxially and selectively formed from the first outer epitaxial feature 228.").
Regarding dependent claim 9, Chung, as previously modified by Cheng, teaches the method of claim 8, wherein the compressive stress material is a tin germanium (SnGe) epitaxial layer ([0029], "In other instances, the first inner epitaxial feature 232 includes germanium tin (GeSn) doped with the second p-type dopant.", [0031], "As shown in FIGS. 9A and 13A, one of the differences between the first inner filler 232 and the second inner filler 234 lies in that the second inner filler 234 is allowed to come in contact with the inner spacer features 226 but the first inner filler 232 is not.', (232 and 234 are the same feature but in different embodiments)).
Regarding dependent claim 14, Chung, as previously modified by Cheng, teaches the method of claim 1. However, as previously combined, they do not teach wherein the plurality of epitaxial growth layers is silicon germanium (SiGe) with a boron (B) dopant.
However, Cheng further teaches wherein the plurality of epitaxial growth layers is silicon germanium (SiGe) with a boron (B) dopant ([0034], "Epitaxial silicon (Si), silicon germanium (SiGe), and/or carbon doped silicon (Si:C) silicon can be doped during deposition (in-situ doped) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by Chung and Cheng with the SiGe of Cheng so as to "allow for selective etching between at least two of them [nanosheets]", (Cheng, [0033]).
Regarding dependent claim 15, Chung, as previously modified by Cheng, teaches the method of claim 1. However, as previously combined, they do not teach wherein the silicon-based material of the plurality of channels is silicon germanium (SiGe).
However, Cheng further teaches wherein the silicon-based material of the plurality of channels is silicon germanium (SiGe) ([0034], "Epitaxial silicon (Si), silicon germanium (SiGe), and/or carbon doped silicon (Si:C) silicon can be doped during deposition (in-situ doped) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by Chung and Cheng with the SiGe of Cheng so as to "allow for selective etching between at least two of them [nanosheets]", (Cheng, [0033]).
Regarding dependent claim 16, Chung, as previously modified by Cheng, teaches the method of claim 1. Cheng further teaches wherein each of the plurality of epitaxial growth layers has a thickness of approximately 4nm to approximately 10nm ([0033], "In illustrative embodiments, the thickness of the sacrificial nanosheets 106 and the channel nanosheets 108 may range from about 3 nanometer (nm) to about 30 nanometers (nm), and more particularly, may range from about 5 nanometers (nm) to about 20 nanometers (nm).").
Claim(s) 4, 5, and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 20210328020 A1), in view of Cheng (US 20210210598 A1) and Nandi (US 20220416032 A1).
Regarding dependent claim 4, Chung, as previously modified by Cheng, teaches the method of claim 2. However, as previously combined, they do not teach wherein a silicide contact layer is formed on the compressive stress material.
However, in the same field of endeavor, Nandi teaches wherein a silicide contact layer is formed on the compressive stress material (Fig. 1, 124, 131; [0025], "In some embodiments, source 124 and drain 126 are epitaxial silicon geranium structures (e.g., epitaxial SiGe) that may include dopants such as boron or gallium.", (This material is described in the present application as an example of "compressive stress material"), [0067], "Contact layer 131 may be substantially pure titanium and silicon (e.g., titanium silicide)...").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chung and Cheng with the silicide contact layer of Nandi so as to "provide source and drain contacts with reduced contact resistance and greater reliability", (Nandi, [0002]).
Regarding dependent claim 5, Chung, as previously modified by Cheng and Nandi, teaches the method of claim 4. Nandi further teaches wherein a contact is formed on the silicide contact layer (Fig. 1, 130; [0067], "Notably, source contact 130 and drain contact 134 include contact layer 131 including co-deposited titanium and silicon.").
Regarding dependent claim 11, Chung, as previously modified by Cheng, teaches the method of claim 6. However, as previously combined, they do not teach wherein a silicide contact layer is formed on the compressive stress material.
However, in the same field of endeavor, Nandi teaches wherein a silicide contact layer is formed on the compressive stress material (Fig. 1, 124, 131; [0025], "In some embodiments, source 124 and drain 126 are epitaxial silicon geranium structures (e.g., epitaxial SiGe) that may include dopants such as boron or gallium.", (This material is described in the present application as an example of "compressive stress material"), [0067], "Contact layer 131 may be substantially pure titanium and silicon (e.g., titanium silicide)...").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chung and Cheng with the silicide contact layer of Nandi so as to "provide source and drain contacts with reduced contact resistance and greater reliability", (Nandi, [0002]).
Regarding dependent claim 12, Chung, as previously modified by Cheng and Nandi, teaches the method of claim 11. However, as previously combined, they do not teach wherein a metal fill material with a compressive stress fills a remaining portion of a source-drain cavity.
However, Cheng further teaches wherein a metal fill material with a compressive stress fills a remaining portion of a source-drain cavity ([0053], "...and depositing electrically conductive material to form contacts (not shown) to the S/D regions 124 of the semiconductor structure 100...the metal fill can be formed by ALD, CVD, and/or PVD to form the electrical contacts.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chung, Cheng, and Nandi with the metal fill material of Cheng so as "to form contacts to the S/D regions", (Cheng, [0053]).
Regarding dependent claim 13, Chung, as previously combined with Cheng and Nandi, teaches the method of claim 12. Cheng further teaches wherein a contact is formed on the metal fill material ([0053], "...where the barrier layer can prevent diffusion and/or alloying of the metal contact fill material with the top source drain material, and/or anode/cathode material...In various embodiments, the metal fill can be formed by ALD, CVD, and/or PVD to form the electrical contacts.").
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 20210328020 A1), in view of Cheng (US 20210210598 A1) and Gluzchenkov (US 20180277483 A1).
Regarding dependent claim 10, Chung, as previously modified by Cheng, teaches the method of claim 6. However, as previously combined, they do not teach wherein the compressive stress material is formed by tin (Sn) implantation and a subsequent anneal process and wherein the Sn implantation uses an ion implantation process, a plasma doping process, or a gas phase doping process.
However, in the same field of endeavor, Gluschenkov teaches wherein the compressive stress material is formed by tin (Sn) implantation and a subsequent anneal process and wherein the Sn implantation uses an ion implantation process, a plasma doping process, or a gas phase doping process (Fig. 10, 902,1002; [0076], "FIG. 10 illustrates a cut-away view following an ion implantation process that implants Sn ions into the trench source/drain region 902 to form an alloyed layer 1002 that includes SiGe:Sn material...Tin solubility in both silicon, germanium, and silicon germanium is less than 1 atomic % resulting in tin precipitates at moderate anneal temperatures for concentration of tin exceeding solubility limit in these materials.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chung and Cheng with the implantation process of Gluschenkov so as "to form an alloyed layer", (Gluschenkov, [0076]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230114789 A1, pertaining to a method for manufacturing a source/dran region with epitaxial processes and nanosheets..
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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