Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 05/15/24. Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement filed on 05/15/24 has been received and is being considered.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C §102(a)(1) and §102(a)(2) as unpatentable over Seong (US 20210082924 A1).
Regarding claim 1, Seong discloses a semiconductor memory device comprising:
a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region (see fig 1, disclosing CR, DR and PR);
a plurality of gate electrodes extending in a first direction, within the substrate of the cell region (see fig 7A where 120 is in cell region);
a plurality of bit lines extending in a second direction crossing the first direction, on the substrate of the cell region and the boundary region (see 140/12 having X and Y extension in fig 7d);
a plurality of buried contacts connected to the substrate of the cell region and between the gate electrodes and between the bit lines (see fig 8a disclosing 170 being buried between 140/147), on the substrate of the cell region (see fig 8 disclosing formation of 170 in cell region);
a dummy buried contact between the bit lines, on the substrate of the boundary region (see formation of 170x formed on 112/114 is insulating in boundary region DR); and
a bit line contact connected to at least one of the bit lines (see para [0107] disclosing bit line contact 170 connected to 140), on the substrate of the boundary region (see fig 8d where 140 spills over to the DR),
wherein the dummy buried contact includes an insulating material (see 170x formed on 112/114 is insulating, see para [0099]).
Regarding claim 2, Seong discloses the semiconductor memory device of claim 1, further comprising: a fence (see fence 180)between a corresponding pair of the bit lines and between a corresponding pair of the buried contacts (see fig 9d disclosing fence alternately arranged with 140), wherein the fence includes a same material as the dummy buried contact (see 170x formed on 112/114 is insulating, see para [0099]).
Regarding claim 3, Seong discloses the semiconductor memory device of claim 2, wherein a first distance from an upper surface of a respective one of the buried contacts to a bottom surface of the respective one of the buried contacts is smaller than a second distance from the upper surface of the respective one of the buried contacts to a bottom surface of the fence (see 112/114/170x is smaller than other 170’s).
Regarding claim 4, Seong discloses the semiconductor memory device of claim 3, wherein a third distance from the upper surface of the respective one of the buried contacts to a bottom surface of the dummy buried contact is equal to the second distance (see other 107, not 107x, are the same height, fig 8c).
Regarding claim 5, Seong discloses the semiconductor memory device of claim 3, wherein a third distance from the upper surface of the respective one of the buried contacts to a bottom surface of the dummy buried contact is different from the second distance (see fig 8c disclosing 112/114/170x has at least three different heights with respect to 170).
Regarding claim 6, Seong discloses he semiconductor memory device of claim 1, further comprising: a cell buffer film between the dummy buried contact and the substrate of the boundary region (see 112/114, disclosing films as a part of the buried contact, 170x).
Regarding claim 7, Seong discloses the semiconductor memory device of claim 1, wherein a level of a bottom surface of a respective one of the buried contacts is different from a level of a bottom surface of the dummy buried contact (see bottoms of 170x vs 170).
Regarding claim 8, Seong discloses the semiconductor memory device of claim 1, wherein a level of a bottom surface of a respective one of the buried contacts is same as a level of a bottom surface of the dummy buried contact (see fig 8a 170y is at same level as 170).
Regarding claim 9, Seong discloses the semiconductor memory device of claim 1, wherein at least a portion of the bit line contact is in contact with the dummy buried contact (see 8b and 8c where 140 and 170x are formed on each other).
Regarding claim 10, Seong discloses the semiconductor memory device of claim 1, wherein the bit line contact includes a first contact connected to one of the bit lines and a second contact connected to another of the bit lines, and at least one of the bit lines is between the first contact and the second contact (see fig 10a where 140 is interconnected).
Regarding claim 11, Seong discloses a semiconductor memory device comprising:
a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region (see figs 7-8 disclosing PR, DR, CR), the cell region including a capacitor 200, the peripheral region including a peripheral circuit element (See PR including circuit elements, figs 7 and 8);
a plurality of gate electrodes (see 120) extending in a first direction, within the substrate of the cell region (see figs 7 and 8 disclosing 120 in substrate);
a plurality of first bit lines extending in a second direction crossing the first direction (see 140 figs 7 and 8), on the substrate of the cell region (over CR);
a plurality of second bit lines connected to the first bit lines (see 140/140D), respectively, on the substrate of the boundary region (in DR);
a plurality of fences and a plurality of buried contacts alternately arranged in the second direction, between the first bit lines (see insulating fences 180);
a dummy buried contact between the second bit lines (see 170x formed on 112/114); and
a bit line contact in contact with at least some of the second bit lines (see figs 7 and 8 disclosing 170 connected to 140), on the substrate of the boundary region (see figs 7 and 8 disclosing 170 connection to 140 with 140 spilling over to DR), wherein a width of a respective one of the first bit lines in the first direction is smaller than a width of a respective one of the second bit lines in the first direction (see 140D and 104d), and
the dummy buried contact includes an insulating material(see 170x formed on 112/114 is insulating, see para [0099]).
Regarding claim 12, Seong discloses the semiconductor memory device of claim 11, further comprising: a pair of second bit line spacers on two opposite sidewalls of each of the second bit lines (see 152), respectively, wherein at least one of the second bit line spacers is in contact with the dummy buried contact (see figs 8b and 8c showing 150 is in contact with 170x).
Regarding claim 13, Seong discloses the semiconductor memory device of claim 12, further comprising: a pair of first bit line spacers on two opposite sidewalls of each of the first bit lines (see 152), respectively, wherein the pair of first bit line spacers are connected to the pair of second bit line spacers, respectively(see figs 8b and 8c showing 150 is in contact with 140/147).
Regarding claim 14, Seong discloses the semiconductor memory device of claim 11, wherein a level of a bottom surface of a respective one of the fences is same as a level of a bottom surface of the dummy buried contact(see fig 8a 170y is at same level as 170).
Regarding claim 15, Seong discloses the semiconductor memory device of claim 11, wherein a material included in the fences is same as a material included in the dummy buried contact(see 112/114, disclosing films as a part of the buried contact, 170x).
Regarding claim 16, Seong discloses the semiconductor memory device of claim 15, wherein a first distance from an upper surface of a respective one of the buried contacts to a bottom surface of the respective one of the buried contacts is smaller than a second distance from the upper surface of the respective one of the buried contacts to a bottom surface of a respective one of the fences(see 112/114/170x is smaller than other 170’s).
Regarding claim 17, Seong discloses the semiconductor memory device of claim 11, further comprising: a cell buffer film between the dummy buried contact and the substrate of the boundary region(see 112/114, disclosing films as a part of the buried contact, 170x).
Regarding claim 18, Seong discloses the semiconductor memory device of claim 11, wherein at least a portion of the bit line contact is in contact with the dummy buried contact(see 8b and 8c where 140 and 170x are formed on each other).
Regarding claim 19, Seong discloses the semiconductor memory device of claim 11, wherein the substrate of the cell region includes impurity regions 210 between the gate electrodes, and the buried contacts are connected to the impurity regions and 140/147, respectively.
Regarding claim 20, Seong discloses a semiconductor memory device comprising: a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region (see fig 1 disclosing PR, DR, CR);
a peripheral circuit element on the substrate of the peripheral region (see elements in PR); a plurality of gate electrodes extending in a first direction (see 120), within the substrate of the cell region (see 120 formed in substrate);
a plurality of bit lines extending in a second direction crossing the first direction, on the substrate of the cell region and the boundary region (see element 120 fig 9d);
a plurality of buried contacts on the substrate of the cell region and spaced apart from each other in the second direction (see 170 spaced apart from each other), the buried contacts connected to the substrate of the cell region (see figs 7-10 disclosing 170), the buried contacts being between the gate electrodes and between the bit lines (170 is between 140 and 120);
a plurality of capacitors connected to the buried contacts (see fig 10a disclosing 200 connected to 170), respectively, on the substrate of the cell region;
a plurality of fences between the buried contacts and between the gate electrodes (see figs 7 disclosing 180), the fences spaced apart from each other in the second direction and being on the substrate of the cell region (see fig 7 and 8 disclosing 180 being spaced out);
a dummy buried contact between the bit lines, on the substrate of the boundary region (see 112/114/170 is in DR); and
a bit line contact connected to at least one of the bit lines (see 170 connected with140, figs 7 and 8), on the substrate of the boundary region (see at least 140 extends into DR), wherein a first distance from an upper surface of a respective one of the buried contacts to a bottom surface of the respective one of the buried contacts is smaller than a second distance from the upper surface of the respective one of the buried contacts to a bottom surface of a respective one of the fences (see 112/114/170x is shorter than 180, see fig 7 and 8), at least a portion of the dummy buried contacts is in contact with the substrate of the boundary region (see 112/114/170 is in DR),
and the dummy buried contacts and the fences include a same material (170x/112/114 same as 180 see para [0093] disclosing 180 being nitride, see para [0071] disclosing nitride film for 114).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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