Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Election/Restrictions
Applicant’s election without traverse of Group I, claims #1-14 in the reply filed on 08/19/26 is acknowledged.
Accordingly, claims #1-14 will be further examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/15/24 was filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) #1-12, 14, is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by WATANABE (U.S. Pub. No, 2023/0276625), hereinafter referred to as "Watanabe".
Watanabe shows, with respect to claim #1, memory device, comprising: an alternating stack of insulating layers (fig. #5, item 32) and electrically conductive layers (fig. #5, item 42) that alternate along a vertical direction (paragraph 0076, 0078) ; memory openings (fig. #6a, item 19) vertically extending through the alternating stack in a memory array region (Paragraph 0096); memory opening fill structures located in the memory openings and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel (fig. #8, item 58) (paragraph 0115); and layer contact via (fig. #15, item 75) structures contacting the electrically conductive layers (paragraph 0150); wherein: each electrically conductive layer within a subset of the electrically conductive layers (Below, fig. #Ex1, item #42) comprises a respective tab portion (Below, fig. #Ex1, item FT1) that laterally protrudes away from the memory array region relative to a respective underlying vertically-neighboring electrically conductive layer and relative to a respective overlying vertically-neighboring electrically conductive layer (paragraph 0138); and a subset of the layer contact via structures contacts a top surface of a respective one of the tab portions (fig. #19A, item 86) (paragraph 0163).
[AltContent: textbox (Conductive Layer; #42)][AltContent: textbox (First Tab area; FT1)]
[AltContent: arrow][AltContent: textbox (Second Tab area; FT2)][AltContent: textbox (42c)][AltContent: ][AltContent: textbox (Stack Width; SW)][AltContent: textbox (42b)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Side Walls; SA)][AltContent: textbox (42a)][AltContent: rect][AltContent: textbox (Tab Width; TW)][AltContent: textbox (Conductor Width; CW)][AltContent: ][AltContent: ][AltContent: connector][AltContent: arrow][AltContent: textbox (Ex1)]
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Watanabe shows, with respect to claim #2, memory device, comprising: wherein: each layer within the alternating stack (Above, fig. #Ex1, item 42) laterally extends along a first horizontal direction (Above, fig. #Ex1, item CW) and has a uniform layer stack width (Above, fig. #Ex1, item SW) along a second horizontal direction in the memory array region; the tab portions of the subset of the electrically conductive layers laterally protrude along the first horizontal direction (Above, fig. #Ex1, item TW); and the tab portions have a respective tab width that is less than the uniform layer stack width (paragraph 0138, 0163).
Watanabe shows, with respect to claim #3, memory device, comprising: wherein: each electrically conductive layer (Above, fig. #Ex1, item 42) within the subset of the electrically conductive layers is located between a respective vertically-neighboring pair of insulating layers (Above, fig. #Ex1, item 32) of the insulating layers; and the respective vertically-neighboring pair of insulating layers have sidewalls (Above, fig. #Ex1, item SA) that laterally extend along the second horizontal direction and are vertically coincident with each other (paragraph 0003, 0075).
Watanabe shows, with respect to claim #4, memory device, wherein each electrically conductive layer (Above, fig. #Ex1, item 42) within the subset of the electrically conductive layers is in direct contact with the respective vertically-neighboring pair of insulating layers (Above, fig. #Ex1, item 32), and has a respective sidewall that is vertically coincident with the sidewalls (Above, fig. #Ex1, item SA) of the respective vertically-neighboring pair of insulating layers (paragraph 0003, 0075).
Watanabe shows, with respect to claim #5, memory device, wherein each electrically conductive layer (fig. #7F, item 42) within the subset of the electrically conductive layers is spaced from the respective vertically-neighboring pair of insulating layers (fig. #7F, item 32) by a respective outer blocking dielectric layer (fig. #7F, item 52), and has a respective sidewall that is laterally offset from the sidewalls of the respective vertically-neighboring pair of insulating layers by a thickness of the respective outer blocking dielectric layer (paragraph 0100-0101).
Watanabe shows, with respect to claim #6, memory device, wherein each electrically wherein a respective first additional insulating layer (fig. #7F, item 32a) that underlies the respective vertically-neighboring pair of insulating layers (fig. #7F, item 32b) and a respective second additional insulating layer that overlies the respective vertically-neighboring pair of insulating layers (fig. #7F, item 32c-d) have sidewalls (Below, fig. #Ex2, item CSW) that laterally extend along the second horizontal direction and are vertically coincident with the sidewalls of the respective vertically-neighboring pair of insulating layers (paragraph 0100-0101).
[AltContent: textbox (d)][AltContent: textbox (c)][AltContent: textbox (b)][AltContent: textbox (a)][AltContent: textbox (d)][AltContent: textbox (c)][AltContent: textbox (b)][AltContent: textbox (a)][AltContent: textbox (Coincided Side Walls; CSW)][AltContent: ][AltContent: textbox (Ex2)]
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Watanabe shows, with respect to claim #7, memory device, wherein the respective underlying vertically-neighboring electrically conductive layer (Above, fig. #Ex1, item #42c) and the respective overlying vertically-neighboring electrically conductive layer (Above, fig. #Ex1, item #42a) are vertically adjacent to the electrically conductive layer (Above, fig. #Ex1, item #42b) that comprises the respective tab portion (paragraph 0100-0101).
Watanabe shows, with respect to claim #8, memory device, wherein: at least one of the respective underlying vertically-neighboring electrically conductive layer (Above, fig. #Ex1, item #42c) and the respective overlying vertically-neighboring electrically conductive layer (Above, fig. #Ex1, item #42a) are not vertically adjacent to the electrically conductive layer (Above, fig. #Ex1, item #42b) that comprises the respective tab portion; and at least two of the vertically adjacent electrically conductive layers in the subset of the electrically conductive layers comprise the respective tab portions that have vertically coincident sidewalls (paragraph 0100-0101).
Watanabe shows, with respect to claim #9, memory device, wherein: the respective tab portion (Above, fig. #Ex1, item #FT1) laterally protrudes away from the memory (Above, fig. #Ex1, item 42a) array region relative to the respective underlying vertically-neighboring electrically conductive layer (Above, fig. #Ex1, item 42b) by a first lateral protrusion distance (paragraph 0138, 0163); the respective tab portion laterally protrudes away from the memory array region relative to the respective overlying vertically-neighboring electrically conductive layer by a second lateral protrusion distance; and the second lateral protrusion distance is the same as the first lateral protrusion distance (paragraph 0100-0101).
Watanabe shows, with respect to claim #10, memory device wherein the respective tab portion (Above, fig. #Ex1, item #FT1) laterally protrudes away from the memory array region relative to a respective first additional electrically conductive layer (Above, fig. #Ex1, item 42b) that underlies the respective underlying vertically-neighboring electrically conductive layer (Above, fig. #Ex1, item 42a), and relative to a respective second additional electrically conductive layer that overlies the respective overlying vertically-neighboring electrically conductive layer (paragraph 0138, 0163); and a sidewall (Above, fig. #Ex2, item CSW) of the respective first additional electrically conductive layer (Above, fig. #Ex2, item 42a), a sidewall of the respective underlying vertically-neighboring electrically conductive layer (Above, fig. #Ex2, item 42b), a sidewall of the respective second additional electrically conductive layer, and a sidewall of the respective overlying vertically-neighboring electrically conductive layer are vertically coincident with each other (paragraph 0100-0101).
Watanabe shows, with respect to claim #11, memory device further comprising a finned dielectric material (fig. #15, item 44) portion that includes laterally-extending dielectric fins that extend into gaps between neighboring pair of insulating layers of the insulating layers (paragraph 0134).
Watanabe shows, with respect to claim #12, memory device, wherein a tab portion of the tab portions (fig. #6a, item 135) (paragraph 0090) of the subset of the electrically conductive layers (fig. #6a, item 42) is vertically spaced (fig. #6a, item 134) from a most proximal overlying one of the laterally-extending dielectric fins by at least one of the insulating layers, and is vertically spaced from a most proximal underlying one of the laterally-extending dielectric fins by at one other one of the insulating layers (paragraph 0085, 0090).
Watanabe shows, with respect to claim #14, memory device, , wherein: a tab portion of the tab portions of the subset of the electrically conductive layers (fig. #7F, item 42) is laterally spaced from the finned dielectric material portion (fig. #7F, item 52) by an etch-stop material portion; and the etch-stop material portion has a top surface, a bottom surface, and a sidewall that contacts the finned dielectric material portion (paragraph 0100-0101).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim #13 is/are rejected under 35 U.S.C. 103 as being unpatentable over WATANABE (U.S. Pub. No, 2023/0276625), hereinafter referred to as "Watanabe" as shown in the rejection of claim #12, and in view of SHIBATA et al., (U.S. Pat. No. 2023/0282633), hereinafter referred to as "Shibata".
Watanabe substantially shows the claimed invention as shown in the rejection of claim #12 above.
Watanabe fails to show, with respect to claim #13, memory device, wherein a tab portion of the tab portions of the subset of the electrically conductive layers has an areal overlap with at least one of the overlying laterally-extending dielectric fins and has an areal overlap with at least one of the underlying laterally-extending dielectric fins.
Shibata teaches, with respect to claim #13, memory device (Below, fig. #Ex3, item 26), wherein a tab portion (Below, fig. #Ex3, item TB) of the tab portions of the subset of the electrically conductive layers has an areal overlap (Below, fig. #Ex3, item SG) with at least one of the overlying laterally-extending dielectric fins and has an areal overlap with at least one of the underlying laterally-extending dielectric fins (paragraph 0079).
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[AltContent: textbox (Spacing; SG)][AltContent: textbox (Tabs; TB)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (26)][AltContent: ][AltContent: textbox (Ex3)]
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It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #13, to modified the invention of Watanabe as modified by the invention of Shibata, which teaches, wherein a tab portion of the tab portions of the subset of the electrically conductive layers has an areal overlap with at least one of the overlying laterally-extending dielectric fins and has an areal overlap with at least one of the underlying laterally-extending dielectric fins, to incorporate a structural condition that would electrical insulation from surrounding layers, as taught by Shibata.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
09/24/2026
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights