Prosecution Insights
Last updated: October 02, 2026
Application No. 18/664,926

STACKED TRANSISTORS WITH VERTICALLY STAGGERED CONTACT VIAS

Non-Final OA §102
Filed
May 15, 2024
Examiner
PHAM, LONG
Art Unit
Tech Center
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1530 granted / 1671 resolved
+31.6% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
40 currently pending
Career history
1697
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
42.7%
+2.7% vs TC avg
§102
39.7%
-0.3% vs TC avg
§112
10.3%
-29.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1671 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-19 in the reply filed on 7/2/26 is acknowledged. Also, there is no response to the species restriction, it is assumed that the elected claims read on the species 1 of fig. 1. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 8, 9, 10, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US pub 20230411397). With respect to claim 1, Xie et al. teach a semiconductor structure, wherein the semiconductor structure comprises (see figs. 1-10, particularly fig. 5 and associated text): a first stacked transistor cell (middle column), the first stacked transistor cell comprising a first backside contact 160 and the first backside contact having a first contact thickness; and a second stacked transistor cell (the left column), the second stacked transistor cell comprising a second backside contact 162, the second backside contact having a second contact thickness different from the first contact thickness. With respect to claim 2, Xie et al. teach the second stacked transistor cell is adjacent to the first stacked transistor cell. See fig. 5 and associated text. With respect to claim 8, Xie et al. teach the second contact thickness is larger than the first contact thickness. See fig. 5 and associated text. With respect to claim 9, Xie et al. teach the first stacked transistor cell further comprises a first top epi 127 and a first bottom epi 112; and the second stacked transistor cell further comprises a second top epi 127 and a second bottom epi 112. See fig. 5 and associated text. With respect to claim 10, Xie et al. teach the first backside contact is directly connected to the first bottom epi; and the second backside contact is directly connected to the second bottom epi. See fig. 5 and associated text. With respect to claim 11, Xie et al. teach the first transistor cell and the second transistor cell further comprise one or more nanosheets. See fig. 5 and associated text. Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US pub 20230411397). With respect to claim 1, Xie et al. teach a semiconductor structure, wherein the semiconductor structure comprises (see figs. 1-10, particularly fig. 5 and associated text): With respect to claim 1, Xie et al. teach a semiconductor structure, wherein the semiconductor structure comprises (see figs. 1-10, particularly fig. 5 and associated text): a first stacked transistor cell (the left column), the first stacked transistor cell comprising a first backside contact 162 and the first backside contact having a first contact thickness; and a second stacked transistor cell (the middle column), the second stacked transistor cell comprising a second backside contact 160, the second backside contact having a second contact thickness different from the first contact thickness. With respect to claim 8, Xie et al. teach the second contact thickness is smaller than the first contact thickness. See fig. 5 and associated text. Claim(s) 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US pub 20230411397). With respect to claim 12, Xie et al. teach a system, wherein the system comprises (see figs. 1-10, particularly fig. 5 and associated text): the semiconductor structure comprises: a first stacked transistor cell (the middle column), the first stacked transistor cell having a first contact thickness (of contact 160), wherein the first stacked transistor cell comprises a first backside contact 160, a first bottom epi 112, and a first top epi 127, and wherein the first backside contact is directly connected to the first bottom epi; and a second stacked transistor cell (the left column), the second stacked transistor cell having a second contact (of contact 162) thickness larger than the first contact thickness, wherein the second transistor cell comprises a second backside contact 162, a second bottom epi 112, and a second top epi 127, and wherein the second backside contact is directly connected to the second bottom epi. Allowable Subject Matter Claims 4-6 and 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having a first stacked transistor cell having a first backside contact and a second stacked transistor cell having a second backside contact, where the thicknesses of the first and second backside contacts are different as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

May 15, 2024
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751320
CHIP-ON-WAFER-ON-BOARD STRUCTURE USING SPACER DIE AND METHODS OF FORMING THE SAME
4y 3m to grant Granted Sep 29, 2026
Patent 12745645
Integrated Circuit Packages and Methods of Forming the Same
3y 8m to grant Granted Sep 22, 2026
Patent 12745684
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
3y 6m to grant Granted Sep 22, 2026
Patent 12740475
SILICON NITRIDE LINER FOR PROMOTION OF MOLD ADHESION IN INTEGRATED CIRCUITS
5y 0m to grant Granted Sep 15, 2026
Patent 12738918
DIE PACKAGE WITH SEALED DIE ENCLOSURES
4y 0m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1671 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month