DETAILED ACTION
This correspondence is in response to the communications received May 15, 2024. Claims 21-40 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 21, the Applicant discloses in Figs. 1B to 2D, a method of manufacturing a magnetic memory element, the method comprising:
etching through a portion of at least one interlevel dielectric (ILD) layer (120), wherein the etching through a portion of the at least one ILD layer exposes at least one metal layer (110, );
depositing a transition metal layer (130) above the at least one metal layer (110);
depositing a tantalum-rich layer (140) above the transition metal layer (above 110);
removing a portion of the tantalum-rich layer (see steps occurring in Fig. 2B to 2C); and
forming a magnetoresistive device (150) above the transition metal layer (above 130), wherein the magnetoresistive device comprises:
a fixed magnetic region (discussed in ¶ 0089, not shown, but understood to be within 150);
a free magnetic region (discussed in ¶ 0089, not shown, but understood to be within 150); and
an intermediate region disposed between the fixed magnetic region and the free magnetic region (discussed in ¶ 0089, not shown, but understood to be within 150),
wherein removing a portion of the tantalum-rich layer (140) includes removing a portion of the transition metal layer disposed above the at least one etched ILD layer (¶ 0043, “regions above metal regions 110 may be etched to form one or more trenches 125 in the ILD layers 120 above metal regions 110”, see steps occurring from Fig. 1B to 2C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 29-31, 37, 35 and 38-40 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 9,691,816) in view of Park et al. (US 10,966,649).
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Regarding claim 29, the prior art of Han discloses in Figs. 1A, 3B, 4B, 5B, 6B, 7B and 8B, a method of manufacturing a magnetic memory element (see title, “Magnetic Memory Devices”), the method comprising:
providing at least one metal layer (130 is a metal, col. 6, lines 35-40);
forming at least one interlevel dielectric (ILD) layer (141, col. 10, lines 50-51, “second lower insulating layer 141”) above the at least one metal layer (141 is vertically above 130);
etching (the specific method of patterning by “etching”, will be addressed in the combination rejection below) through a first portion of at least one interlevel dielectric (ILD) layer (in Fig. 4B, opening “OP” created in “lower insulating layer 141”, col. 10, lines 50-56),
depositing a transition metal layer (150, “The lower electrode 150 may include … transition metals (e.g., titanium or tantalum)”, col. 7, lines 3-6) above the at least one metal layer (150 on 130);
forming a magnetoresistive device (160) above the transition metal layer (above 150), wherein the magnetoresistive device (160) includes:
a fixed magnetic region (one of 162 or 164, col. 16, lines 47-56);
a free magnetic region (other of one of 162 or 164, col. 16, lines 47-56); and
an intermediate region (“a tunnel barrier (e.g. tunnel insulating) pattern 164”, col. 7, lines 54-56) disposed between the fixed magnetic region and the free magnetic region (164 is shown between 162 and 164).
Han does not specify wherein,
“etching through a first portion of at least one interlevel dielectric (ILD) layer, wherein the etching exposes at least one metal layer”.
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Park discloses in the sequence of steps from Fig. 11A to 11B, etching through a first portion of at least one interlevel dielectric (ILD) layer, wherein the etching through a first portion of the at least one ILD layer exposes at least one metal layer (“FIG. 11B … The dielectric materials 1106, 1108 may be etched according to the patterned layer 1104 to form the opening 1110.”, col. 15, lines 7-17).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “etching through a first portion of at least one interlevel dielectric (ILD) layer, wherein the etching exposes at least one metal layer”, as disclosed by Park in the system of Han, for the purpose of creating a pattern opening in an insulation layer to allow for electrical connection to the lower metal layer, for subsequent connection to the memory site which will be formed thereafter. G. TSM: Teaching, Suggestion, Motivation Test.
Regarding claim 30, Han et al. disclose the method of claim 29, and Han discloses, further comprising forming one or more ILD layers (insulating layer 120) on a substrate comprising the at least one metal layer (130 within 120, which both are formed on 110).
Regarding claim 31, Han et al. disclose the method of claim 29, and Han discloses, further comprising removing a portion of the transition metal layer (150 formed by CMP, col. 11, lines 8-21, step of partial removal of portions of 150 as can be seen in step from Fig. 5B to 6B).
Regarding claim 34, Han et al. disclose the method of claim 29, and Han discloses, wherein the magnetoresistive device has a diameter greater than a diameter of the transition metal layer (160 has a wider diameter than 150).
Regarding claim 35, the prior art of Han discloses in Figs. 1A, 3B, 4B, 5B, 6B, 7B and 8B, a method of manufacturing a magnetic memory element (see title, “Magnetic Memory Devices”), the method comprising:
providing at least one metal layer (130, col. 6, lines 35-38, “The lower contact 130 may include at least one of metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), or transition metals (e.g., titanium or tantalum).”);
forming at least one interlevel dielectric (ILD) layer (140, col. 6, lines 40-42, “The insulating structure 140 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride”) above the at least one metal layer (140 is above 130);
etching (the specific method of patterning by “etching”, will be addressed in the combination rejection below) through a portion of at least one interlevel dielectric (ILD) layer (142/141, in Figs. 1A or 4B, “opening OP” created in “lower insulating layer 141”, col. 10, lines 50-56), wherein the etching through a potion of the at least one ILD layer exposes the at least one metal layer (top surface of 130 exposed by OP in 141) and forms a trench (the opening is a trench shaped opening);
depositing a transition metal layer (150, “The lower electrode 150 may include … transition metals (e.g., titanium or tantalum)”, col. 7, lines 3-6) above the at least one metal layer (150 on 130); and
forming a magnetoresistive device (160, col. 6, line 23, “a magnetic tunnel junction pattern 160”) above the transition metal layer (above 150), wherein the magnetoresistive device (160) includes:
a fixed magnetic region (one of 162 or 164, col. 16, lines 47-56);
a free magnetic region (other of one of 162 or 164, col. 16, lines 47-56); and
an intermediate region (“a tunnel barrier (e.g. tunnel insulating) pattern 164”, col. 7, lines 54-56) disposed between the fixed magnetic region and the free magnetic region (164 is shown between 162 and 164).
Han does not specify wherein,
“etching through a first portion of at least one interlevel dielectric (ILD) layer, wherein the etching exposes at least one metal layer”.
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Park discloses in the sequence of steps from Fig. 11A to 11B, etching through a first portion of at least one interlevel dielectric (ILD) layer, wherein the etching through a first portion of the at least one ILD layer exposes at least one metal layer (“FIG. 11B … The dielectric materials 1106, 1108 may be etched according to the patterned layer 1104 to form the opening 1110.”, col. 15, lines 7-17).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “etching through a first portion of at least one interlevel dielectric (ILD) layer, wherein the etching exposes at least one metal layer”, as disclosed by Park in the system of Han, for the purpose of creating a pattern opening in an insulation layer to allow for electrical connection to the lower metal layer, for subsequent connection to the memory site which will be formed thereafter. G. TSM: Teaching, Suggestion, Motivation Test.
Regarding claim 38, Han et al. disclose the method of claim 35, and Han discloses, wherein the magnetoresistive device has a diameter greater than a diameter of the transition metal layer (160 has a wider diameter than 150).
Regarding claim 39, Han et al. disclose the method of claim 35, and Han discloses in Fig. 1A, further comprising depositing a cap layer (“insulating pattern 144”, col. 7, line 12) above the at least one metal layer (130) and forming at least one interlevel dielectric (ILD) layer (142) above the at least one metal layer (vertically above 130).
Regarding claim 40, Han et al. disclose the method of claim 35, and Han discloses, further comprising removing a portion of the transition metal layer (150 formed by CMP, col. 11, lines 8-21, step of partial removal of portions of 150 as can be seen in step from Fig. 5B to 6B).
Claims 32 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 9,691,816) in view of Park et al. (US 10,966,649) in view of Peng et al. (US 10,862,023).
Regarding claims 32 and 36, Han et al. disclose the method of claim 29 or 35, however Han does not disclose,
(for claim 32) “further comprising depositing a tantalum-rich layer that has a diameter greater than a diameter of the transition metal layer.”, and
(for claim 36) “further comprising a depositing a tantalum-rich layer, wherein the tantalum-rich layer has a diameter greater than a diameter of the transition metal layer.”
Peng discloses in Fig. 3C, further comprising depositing a tantalum-rich layer (121b’ includes Ta or Tan, col. 8, lines 20-25) that has a diameter greater than a diameter of the transition metal layer (the transition metal layer is 122a, which includes titanium, col. 7, line 53-59. The diameter of 121b’ is shown in Fig. 3C, as wider than that of diameter of 122a).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation,
(for claim 32) “further comprising depositing a tantalum-rich layer that has a diameter greater than a diameter of the transition metal layer.”, and
(for claim 36) “further comprising a depositing a tantalum-rich layer, wherein the tantalum-rich layer has a diameter greater than a diameter of the transition metal layer.”, as disclosed by Peng in the system of Han, for the purpose of improving adhesion between the transition metal layer and the bottom electrode of the device. G. TSM: Teaching, Suggestion, Motivation Test.
Claims 33 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 9,691,816) in view of Park et al. (US 10,966,649) in view of Kim et al. (US 9,362,486).
Regarding claims 33 and 37, Han et al. disclose the method of claim 29 or 35, however Han does not disclose,
(for claim 33) “wherein the magnetoresistive device includes a synthetic anti-ferromagnetic structure.”, and
(for claim 37) “wherein the magnetoresistive device includes a synthetic anti-ferromagnetic structure.”
Kim discloses in col. 3, lines 61-64, “The magnetic tunnel junction pattern 400 may be located on the lower plug 300. The magnetic tunnel junction pattern 400 may include a synthetic anti-ferromagnetic (SAF) structure.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation,
(for claim 33) “wherein the magnetoresistive device includes a synthetic anti-ferromagnetic structure.”, and
(for claim 37) “wherein the magnetoresistive device includes a synthetic anti-ferromagnetic structure.”, as disclosed by Kim in the system of Han, for the purpose of providing a layer of magnetic materials which can maintain unchanged magnetizations due to higher switching yields, and further the material may reduce critical current density and enhance thermal stability of magnetic memory devices. G. TSM: Teaching, Suggestion, Motivation Test.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-40 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-7, 9, 14, 19 and 20 of U.S. Patent No. 12,022,738.
Although the claims at issue are not identical, they are not patentably distinct from each other because the parent application contains each of the instant application’s claimed limitations. It is noted here, that the repetition of the claim language in the following rejections will be included only when it is not readily apparent how the claims share similar limitations or when obviousness type rejection is required. When claim numbers are only stated, it should be readily apparent to the reader, which limitations are shared by the instant application and the parent application.
Claim limitation(s) of the instant application (IA)
Claim limitation(s) of the ‘738 patent
21. (New) A method of manufacturing a magnetic memory element, the method comprising:
A. etching through a portion of at least one interlevel dielectric (ILD) layer, wherein the etching through a portion of the at least one ILD layer exposes at least one metal layer;
B. depositing a transition metal layer above the at least one metal layer;
C. depositing a tantalum-rich layer above the transition metal layer;
D. removing a portion of the tantalum-rich layer; and
E. forming a magnetoresistive device above the transition metal layer, wherein the magnetoresistive device comprises:
F. a fixed magnetic region;
G. a free magnetic region; and
H. an intermediate region disposed between the fixed magnetic region and the free magnetic region,
I. wherein removing a portion of the tantalum-rich layer includes removing a portion of the transition metal layer disposed above the at least one etched ILD layer.
1. A method of manufacturing a magnetic memory element, the method comprising:
A. etching through a first portion of at least one interlevel dielectric (ILD) layer, wherein the etching through a first portion of the at least one ILD layer exposes at least one metal layer;
B. depositing a transition metal layer above the at least one metal layer via selective atomic-layer deposition;
C. depositing a tantalum-rich layer above the transition metal layer;
D. removing a portion of the tantalum-rich layer by chemical-mechanical planarization; and
E. forming a magnetoresistive device above the transition metal layer, wherein the magnetoresistive device comprises:
F. a fixed magnetic region;
G. a free magnetic region; and
H. an intermediate region disposed between the fixed magnetic region and the free magnetic region;
wherein at least a portion of the transition metal layer is disposed above the at least one etched ILD layer; and
I. removing a portion of the tantalum-rich layer by chemical-mechanical planarization includes removing a portion of the transition metal layer disposed above the at least one etched ILD layer.
22. (New) The method of claim 21, further comprising forming one or more ILD layers on a substrate comprising the at least one metal layer.
Claim 2.
23. (New) The method of claim 22, further comprising depositing a cap layer above the at least one metal layer prior to the forming of the one or more ILD layers.
Claim 3.
24. (New) The method of claim 21, further comprising removing a portion of the transition metal layer.
Claim 4.
25. (New) The method of claim 21, wherein the tantalum-rich layer has a diameter greater than a diameter of the transition metal layer.
Claim 5.
26. (New) The method of claim 21, wherein the magnetoresistive device includes a synthetic anti-ferromagnetic structure.
Claim 6.
27. (New) The method of claim 21, wherein the magnetoresistive device has a diameter greater than a diameter of the transition metal layer.
Claim 7.
28. (New) The method of claim 21, wherein at least a portion of the transition metal layer is disposed above the at least one etched ILD layer.
Last clause of claim 1.
29. (New) A method of manufacturing a magnetic memory element, the method comprising:
A. providing at least one metal layer;
B. forming at least one interlevel dielectric (ILD) layer above the at least one metal layer;
C. etching through a portion of the at least one ILD layer;
D. depositing a transition metal layer above the at least one metal layer; and
E. forming a magnetoresistive device above the transition metal layer, wherein the magnetoresistive device comprises:
F. a fixed magnetic region;
G. a free magnetic region; and
H. an intermediate region disposed between the fixed magnetic region and the free magnetic region.
9. A method of manufacturing a magnetic memory element, the method comprising:
C. etching through a first portion of B. at least one interlevel dielectric (ILD) layer, wherein the etching exposes A. at least one metal layer;
depositing a cap layer above the at least one metal layer;
forming one or more ILD layers on a substrate, wherein the substrate includes the at least one metal layer and an oxide layer;
forming a via, wherein forming the via includes:
D. depositing a transition metal layer above the at least one metal layer using atomic-layer deposition; and
depositing a tantalum-rich layer above the transition metal layer; and
E. forming a magnetoresistive device above the via, wherein the magnetoresistive device includes:
F. a fixed magnetic region;
G. a free magnetic region; and
H. an intermediate region disposed between the fixed magnetic region and the free magnetic region;
wherein a diameter of the transition metal layer is less than a diameter of the magnetoresistive device.
30. (New) The method of claim 29, further comprising forming one or more ILD layers on a substrate comprising the at least one metal layer.
Clause 3 of claim 9.
31. (New) The method of claim 29, further comprising removing a portion of the transition metal layer.
Claim 19.
32. (New) The method of claim 29, further comprising depositing a tantalum-rich layer that has a diameter greater than a diameter of the transition metal layer.
Clause 6 and last clause of claim 9.
33. (New) The method of claim 29, wherein the magnetoresistive device includes a synthetic anti-ferromagnetic structure.
Claim 20.
34. (New) The method of claim 29, wherein the magnetoresistive device has a diameter greater than a diameter of the transition metal layer.
Last clause of claim 9.
35. (New) A method of manufacturing a magnetic memory element, the method comprising:
A. providing at least one metal layer;
B. forming at least one interlevel dielectric (ILD) layer above the at least one metal layer;
C. etching through a portion of the at least one ILD layer, wherein the etching through a portion of the at least one ILD layer exposes the at least one metal layer and forms a trench; [this portion disclosed in claim 14]
D. depositing a transition metal layer above the at least one metal layer; and
E. forming a magnetoresistive device above the transition metal layer, wherein the magnetoresistive device comprises:
F. a fixed magnetic region;
G. a free magnetic region; and
H. an intermediate region disposed between the fixed magnetic region and the free magnetic region.
9. A method of manufacturing a magnetic memory element, the method comprising:
C. etching through a first portion of B. at least one interlevel dielectric (ILD) layer, wherein the etching exposes A. at least one metal layer;
depositing a cap layer above the at least one metal layer;
forming one or more ILD layers on a substrate, wherein the substrate includes the at least one metal layer and an oxide layer;
forming a via, wherein forming the via includes:
D. depositing a transition metal layer above the at least one metal layer using atomic-layer deposition; and
depositing a tantalum-rich layer above the transition metal layer; and
E. forming a magnetoresistive device above the via, wherein the magnetoresistive device includes:
F. a fixed magnetic region;
G. a free magnetic region; and
H. an intermediate region disposed between the fixed magnetic region and the free magnetic region;
wherein a diameter of the transition metal layer is less than a diameter of the magnetoresistive device.
14. The method of claim 9, wherein etching through a first portion of at least one ILD layer forms a trench having a height, and the height of the trench is greater than a thickness of the transition metal layer.
36. (New) The method of claim 35, further comprising a depositing a tantalum-rich layer, wherein the tantalum-rich layer has a diameter greater than a diameter of the transition metal layer.
Clause 6 and last clause of claim 9.
37. (New) The method of claim 35, wherein the magnetoresistive device includes a synthetic anti-ferromagnetic structure.
Claim 20.
38. (New) The method of claim 35, wherein the magnetoresistive device has a diameter greater than a diameter of the transition metal layer.
Last clause of claim 9.
39. (New) The method of claim 35, further comprising depositing a cap layer above the at least one metal layer and forming at least one interlevel dielectric (ILD) layer above the at least one metal layer.
Clauses 2 and 3 of claim 9.
40. (New) The method of claim 35, further comprising removing a portion of the transition metal layer.
Claim 19.
REASONS FOR ALLOWANCE
Claims 21-28 are potentially allowable, provided that the double patenting rejection is overcome.
The following is an Examiner's statement of reasons for allowance: The method of manufacturing a magnetic memory element as recited in the claims of the instant invention fail to be taught by the prior art cited of interest.
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Regarding claim 21, the prior art of Han et al. (US 9,691,816) discloses in Fig. 1A (provided above) a method of manufacturing a magnetic memory element, but fails to disclose the specific characteristic recited in the claims of the instant invention e.g. the combination of methods that etch a portion of the interlevel dielectric layer, exposing the one metal layer, depositing transition metal layer, depositing a tantalum-rich layer, removing a portion of the tantalum-rich layer, forming a magnetoresistive device with fixed magnetic region, free magnetic region, intermediate region.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893