DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
However, should applicant desire to perfect the priority claim, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on May 15, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner except as otherwise indicated.
Drawings
4. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: "OL" mentioned on Pg 7 [0057]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-2, 8-11, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Im et al (US 2023/0253362 A1, hereafter Im).
Regarding claim 1, Im discloses a semiconductor frame (Fig. 2 180+210), comprising:
a lead frame (Figs. 1 and 2 top 182+210; [0032]) that comprises a mounting portion (Figs. 1 and 2 top 182; [0028]) configured to mount a semiconductor element (Fig. 2 110; [0028]), a wiring portion (Fig. 2 210a; [0032]) spaced apart from the mounting portion (top 182), and a lead-out portion (Fig. 2 210b; [0032]) that extends from the wiring portion (210a);
and an insulating layer (Figs. 1 and 2 181; [0027]) that overlaps the mounting portion (top 182) of the lead frame (top 182+210), and is disposed in a nonoverlapping manner (Fig. 2) with regard to the lead-out portion (210b) of the lead frame (top 182+210).
Regarding claim 2, Im discloses the semiconductor frame of claim 1, further comprising a protective layer (Figs. 1 and 2 bottom 182; [0027]) that overlaps the insulating layer (181),
wherein the insulating layer (181) is disposed (Fig. 2) between the lead frame (top 182+210; [0032]) and the protective layer (bottom 182).
Regarding claim 8, Im discloses the semiconductor frame of claim 1, wherein the insulating layer (181) comprises a ceramic material ([0027]).
Regarding claim 9, Im discloses a semiconductor package (Fig. 2 200), comprising:
a first semiconductor frame (Figs. 1 and 2 181+top 182+210; [0032]) comprising a first lead frame (Figs. 1 and 2 top 182+210; [0032]) and a first insulating layer (Fig. 1 and 2 181; [0027]) disposed below the first lead frame (top 182+210);
a second semiconductor frame (Figs. 1 and 2 141+bottom 142; [0032]) comprising a second lead frame (Figs. 1 and 2 bottom 142; [0032]) that faces the first lead frame (top 182+210), and a second insulating layer (Figs. 1 and 2 141; [0032]) disposed on the second lead frame (bottom 142);
a semiconductor element (Fig. 2 110; [0028]) disposed between the first semiconductor frame (top 182+210) and the second semiconductor frame (bottom 142);
and a molding portion (Fig. 2 200m; [0034]) that surrounds and seals (Fig. 2) at least a portion of the first semiconductor frame (181+top 182+210), at least a portion of the second semiconductor frame (141+bottom 142), and the semiconductor element (110).
Regarding claim 10, Im discloses the semiconductor package of claim 9, wherein the first lead frame (top 182 + 210) comprises a mounting portion (Fig. 2 top 182; [0028]) configured to mount ([0028]) the semiconductor element (110), a wiring portion (Fig. 2 210a; [0032]) spaced apart (112a separates 210a from top 182) from the mounting portion (top 182), and a lead-out portion (Fig. 2 210b; [0032]) that extends (Fig. 2) from the wiring portion (210a),
and wherein the first insulating layer (181) and the second insulating layer (141) are disposed to overlap (Fig. 2) the mounting portion (top 182) of the first lead frame (181+top 182+210), and are disposed in a nonoverlapping manner (Fig. 2) with regard to the lead-out portion (210b) of the first lead frame (181+top 182+210).
Regarding claim 11, Im discloses the semiconductor package of claim 9, further comprising:
a first protective layer (Figs. 1 and 2 bottom 182; [0027]) disposed below the first insulating layer (181);
and a second protective layer (Figs. 1 and 2 top 142; [0027]) disposed on the second insulating layer (141).
Regarding claim 18, Im discloses semiconductor package of claim 9, wherein each of the first insulating layer (181) and the second insulating layer (141) comprises a ceramic material ([0027]).
Regarding claim 19, Im discloses the semiconductor package of claim 18, wherein a surface of the first protective layer (bottom surface of bottom 182) is exposed to an external environment without being surrounded (Fig. 2; [0052]) by the molding portion (200m).
Regarding claim 20, Im discloses the semiconductor package of claim 19, wherein the lead-out portion (210b) is exposed to the external environment without being surrounded (Fig. 2; [0052]) by the molding portion (200m).
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
8. Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Im as applied to claim 1 above, and further in view of Kamiya et al (US 2023/0170278 A1, hereafter Kamiya).
Regarding claim 3¸ Im discloses the semiconductor frame of claim 2, wherein the protective layer (bottom 182) comprises a metal material ([0027]).
Im does not disclose the insulating layer comprises polyimide. However, Im does disclose the insulating layer can be made of a polymer ([0027]).
Kamiya discloses an insulating layer (Fig. 2 20) comprises polyimide ([0030]). Kamiya is analogous to Im in the field of semiconductor power devices.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make the insulating layer of Im with the polyimide material of Kamiya to provide a flexible thermoset insulating layer.
Regarding claim 6, Im and Kamiya disclose the semiconductor frame of claim 3, wherein the protective layer (bottom 182) comprises a copper clad laminate (Im [0027]).
Im discloses the protective layer may be made electrically conductive materials and can additionally include a copper layer ([0027]).
9. Claim 4-5 is rejected under 35 U.S.C. 103 as being unpatentable over Im and Kamiya as applied to claim 3 above, and further in view of Rizza et al (US 2017/0064808 A1, hereafter Rizza).
Regarding claim 4¸ Im and Kamiya discloses the semiconductor frame of claim 3, wherein the protective layer (bottom 182) comprises a metal ([0027]).
Im and Kamiya do not disclose the metal to be a metal foil.
Rizza discloses the thickness of the protective layer (Fig. 2 47) to be between 0.12 mm to 0.5 mm. It is known in the art that the thickness of metal foil may range from 0.035 to 0.25 mm, as evidenced by Okamoto et al (US 2006/0258055 A1) ([0005]). Rizza is analogous to Im and Kamiya in the field of semiconductor power devices.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make the protective layer of Im and Kamiya from a metal foil within the thickness range disclosed by Rizza to fit the desired device size parameters.
Regarding claim 5, Im, Kamiya, and Rizza disclose the semiconductor frame of claim 4, wherein a thickness of the insulating layer (Im 181) is substantially equal to or greater than (Rizza [0041]) a thickness of the protective layer (Im bottom 182).
Rizza discloses the thickness of the insulating layer (Fig. 2 46) is substantially equal to or greater than ([0041]) the thickness of the protective layer (Fig. 2 47).
10. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Im and Kamiya as applied to claim 6 above, and further in view of Rizza.
Regarding claim 7, Im and Kamiya disclose the semiconductor frame of claim 6.
Im and Kamiya do not disclose a thickness of the protective layer is substantially equal to or greater than a thickness of the insulating layer.
Rizza discloses the thickness of the protective layer (Fig. 2 47) is substantially equal to or greater than ([0041]) the thickness of the insulating layer (Fig. 2 46).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the thicknesses of the insulating and protective layers of Im and Kamiya via routine optimization to achieve the desired relationship and sufficient heat dissipation for the device.
11. Claims 12-13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Im as applied to claim 11 above, and further in view of Kamiya.
Regarding claim 12, Im discloses the semiconductor package of claim 11, wherein each of the first protective layer and the second protective layer comprises a metal material.
Im does not disclose each of the first insulating layer and the second insulating layer comprises polyimide. However, Im does disclose the insulating layer can be made of a polymer ([0027]).
Kamiya discloses an insulating layer (Fig. 2 20) comprises polyimide ([0030]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make the insulating layer of Im with the polyimide material of Kamiya to provide a flexible thermoset insulating layer.
Regarding claim 13, Im and Kamiya disclose the semiconductor package of claim 12, wherein a surface of the first protective layer (bottom 182) is exposed to an external environment without being surrounded (Im Fig. 2; [0052]) by the molding portion (200m).
Regarding claim 16, Im and Kamiya disclose the semiconductor package of claim 13, wherein each of the first protective layer (bottom 182) and the second protective layer (top 142) comprises a copper clad laminate (Im [0027).
Im discloses the protective layers may be made electrically conductive materials and can additionally include a copper layer ([0027]).
12. Claim 14-15 is rejected under 35 U.S.C. 103 as being unpatentable over Im and Kamiya as applied to claim 13 above, and further in view of Rizza.
Regarding claim 14, Im and Kamiya disclose the semiconductor package of claim 13, wherein each of the first protective layer (bottom 182) and the second protective layer (top 142) comprises a metal ([0027]).
Im and Kamiya do not disclose the metal to be a metal foil.
Rizza discloses the thickness of the protective layer (Fig. 2 47) to be between 0.12 mm to 0.5 mm. It is known in the art that the thickness of metal foil may range from 0.035 to 0.25 mm, as evidenced by Okamoto et al (US 2006/0258055 A1)([0005]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make the protective layers of Im and Kamiya from a metal foil within the thickness range disclosed by Rizza to fit the desired device size parameters.
Regarding claim 15, Im, Kamiya, and Rizza disclose the semiconductor package of claim 14, wherein thicknesses of the first insulating layer (Im 181) and the second insulating layer (Im 141) are substantially equal to or greater than (Rizza [0041]) thicknesses of the first protective layer (Im bottom 182) and the second protective layer (Im top 142).
Rizza discloses the thickness of the insulating layer (Fig. 2 46) is substantially equal to or greater than ([0041]) the thickness of the protective layer (Fig. 2 47).
13. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Im and Kamiya as applied to claim 16 above, and further in view of Rizza.
Regarding claim 17, Im and Kamiya disclose the semiconductor package of claim 16.
Im and Kamiya do not disclose wherein thicknesses of the first protective layer and the second protective layer are substantially equal to or greater than thicknesses of the first insulating layer and the second insulating layer.
Rizza discloses the thickness of the protective layer (Fig. 2 47) is substantially equal to or greater than ([0041]) the thickness of the insulating layer (Fig. 2 46).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the thicknesses of the first and second insulating layers and the first and second protective layers of Im and Kamiya via routine optimization to achieve the desired relationship and sufficient heat dissipation for the device
Conclusion
14. The following art made of record and not relied upon is pertinent to applicant’s disclosure.
Sugiura et al (US 2020/0194358 A1) discloses a semiconductor module with semiconductor devices encapsulated in a molding portion between two lead frames
Matsuzawa et al (US 2020/0176354 A1) discloses a power conversion apparatus with a semiconductor device encapsulated in a molding portion between two lead frames with an insulating layer and a protection layer
Hirano et al (US 2002.0096759 A1) discloses a lead frame and a heat sink
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL B SUN whose telephone number is (571)699-0231. The examiner can normally be reached Mon-Fri 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL B SUN/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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