DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame (US 2021/0202500) in view of Li (2023/0369218) and Lilak (US 2020/0266218).
Regarding claim 1, Chanemougame discloses a semiconductor device (Figs.4A-4D; [0050]-[0053]) comprising: a lower interlayer insulating layer (note: dark areas between VSS and VDD); an insulating pattern extending (note: hatched layer in Fig. 4C below (426) and extending below the source/drain regions) in a first horizontal direction (along cut direction “B” in Figs 4A and 4C) on an upper surface of the lower interlayer insulating layer (Figs. 4C, 4D); a first plurality of lower nanosheets (note: lower source/drain regions in transistor 406 in Fig. 4C and 4B) and a second plurality of lower nanosheets spaced apart from each other in the first horizontal direction (note: ;lower source/drain region of transistor (406) in Fig.4C ; 4B); a first plurality of middle nanosheets and a second plurality of middle nanosheets spaced apart from each other in the first horizontal direction (note: cut direction “B” in Figs. 4A, 4C), wherein the first plurality of middle nanosheets and the second plurality of middle nanosheets are arranged on the first plurality of lower nanosheets and the second plurality of lower nanosheets, respectively (Fig. 4C, Fig. 4B ;note: similar NS shapes in the lower part of Fig.4A belonging to adjacent mirrored SRAM cells); a first plurality of upper nanosheets and a second plurality of upper nanosheets spaced apart from each other in the first horizontal direction, wherein the first plurality of upper nanosheets and the second plurality of upper nanosheets are arranged on the first plurality of middle nanosheets and the second plurality of middle nanosheets, respectively (Fig. 4C, 4B);; a second stack separation layer (see cross-hatched layer in Fig. 4B) disposed between the first plurality of middle nanosheets and the first plurality of upper nanosheets and between the second plurality of middle nanosheets and the second plurality of upper nanosheets (Figs. 4A, 4B;) ; a first gate electrode (408) extending, wherein the first gate electrode surrounds the first plurality of lower nanosheets, the first plurality of middle nanosheets, and the first plurality of upper nanosheets; a second gate electrode(422) extending in the second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the first horizontal direction, and the second gate electrode surrounds the second plurality of lower nanosheets, the second plurality of middle nanosheets and the second plurality of upper nanosheets; a first middle source/drain region (418)/(414) contacting both sidewalls of the first plurality of middle nanosheets in the first horizontal direction (Fig.4B, 4C); a second middle source/drain region (418)/(414) contacting both sidewalls of the second plurality of middle nanosheets in the first horizontal direction; and a middle source/drain contact (Fig.4C, numeral 428) disposed between the first middle source/drain region and the second middle source/drain region, wherein the middle source/drain contact (428) is electrically connected to the first and second middle source/drain regions (418)/(414), and the middle source/drain contact penetrates the lower interlayer insulating layer (note: dark areas in Fig. 4D) in a vertical direction, wherein an upper surface of the middle source/drain contact is formed lower than a bottom surface of a lowermost nanosheet of the first plurality of upper nanosheets (Fig. 4C; note: the upper surface of the middle source/drain contact is lower that the bottom surface of the upper source/drain regions and lower than a bottom surface of the lowermost of the upper nanosheets, Fig.4B).
Chanemougame does not disclose (1) that the first plurality of lower nanosheets and a second plurality of lower nanosheets is on the insulating pattern; (2) a second horizontal direction different from the first horizontal direction; (3) a first stack separation layer disposed between the first plurality of lower nanosheets and the first plurality of middle nanosheets and between the second plurality of lower nanosheets and the second plurality of middle nanosheets.
Regarding element (1), Li however discloses that the first plurality of lower nanosheets and a second plurality of lower nanosheets is on the insulating pattern ([0046]; Fig. 9, numeral 136).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Chanemougame with Li to have the first plurality of lower nanosheets and a second plurality of lower nanosheets is on the insulating pattern for the purpose of isolating bottom FET device from the device substrate (Li, [0046]).
Regarding element (2), Chanemougame discloses that the common middle source/drain contact (428, LI_T) in Fig, 4C connects two transistors adjacent in a direction perpendicular to the channel direction.
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to have a second horizontal direction different from the first horizontal direction for the purpose of layout optimization directed to a particular circuit.
Regarding element (3), Lilak however discloses a first stack separation layer disposed between the first plurality of lower nanosheets and the first plurality of middle nanosheets and between the second plurality of lower nanosheets and the second plurality of middle nanosheets ([0027]; Fig.1, numeral 108).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Chanemougame with Lilak to have a first stack separation layer disposed between the first plurality of lower nanosheets and the first plurality of middle nanosheets and between the second plurality of lower nanosheets and the second plurality of middle nanosheets for the purpose of decreasing gate-source/drain fringe capacitance (Lilak, [0027]).
Regarding claim 2, Chanemougame discloses wherein the middle source/drain contact includes a first portion disposed between the first and second middle source/drain regions, and a second portion disposed below the first portion, and wherein a width of the first portion of the middle source/drain contact in the first horizontal direction is greater than a width of the second portion of the middle source/drain contact in the first horizontal direction (Fig. 4C, note: tapered shape of the lower, contact-like portion).
Regarding claim 3, Chanemougame discloses wherein a width of the first portion of the middle source/drain contact in the second horizontal direction is greater than a width of the second portion of the middle source/drain contacts in the second horizontal direction Fig. 4C, note: tapered shape of the lower, contact-like portion).
Regarding claim 9, Chanemougame discloses wherein the first gate electrode (408) is integrally formed (Fig.4A; note: “integrally formed” is a product-by-process limitaiton. And according to MPEP 2113, I, "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) “).
Regarding claim 10, Chanemougame does not disclose wherein the middle source/drain contact includes: a contact barrier layer forming sidewalls and an upper surface of the middle source/drain contact, and a contact filling layer filling a gap in the contact barrier layer.
Li however discloses a contact barrier layer forming sidewalls and an upper surface of the middle source/drain contact, and a contact filling layer filling a gap in the contact barrier layer (Fig.4; [0048]).
It would have been therefore obvious to one of ordinary skill in the art the time the invention was filed to have a contact barrier layer forming sidewalls and an upper surface of the middle source/drain contact, and a contact filling layer filling a gap in the contact barrier layer for the purpose of improving adhesion (Li, [0048]).
Allowable Subject Matter
Claims 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest a first insulating layer extending in the second horizontal direction between the first and second lower source/drain regions, wherein the first insulating layer surrounds sidewalls of the second portion of the middle source/drain contact as required by claim 4.
The search of the prior art does not disclose or reasonably suggest a first middle gate electrode spaced apart from the first lower gate electrode in the vertical direction, the first middle gate electrode surrounding the first plurality of middle nanosheets, and a first upper gate electrode spaced apart from the first middle gate electrode in the vertical direction, the first upper gate electrode surrounding the first plurality of upper nanosheets as required by claim 7.
The search of the prior art does not disclose or reasonably suggest he first upper gate electrode surrounding the first plurality of middle nanosheets and the first plurality of upper nanosheets as required by claim 8.
The search of the prior art does not disclose or reasonably suggest a first insulating layer extending in the second horizontal direction between the first plurality of lower nanosheets and the second plurality of lower nanosheets; and a middle source/drain contact including a first portion disposed on an upper surface of the first insulating layer between the first and second middle source/drain regions, and a second portion connected to the first portion by penetrating the first insulating layer in a vertical direction as required by independent claims 11 and 17.
Conclusion
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/JULIA SLUTSKER/ Primary Examiner, Art Unit 2891
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