DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The IDS filed on May 15th, 2024 has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor device comprising subtractive power lines with wrap-around power plane.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-12, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lanzillo et al. (U.S. Pub. 2022/0406717).
In re claim 1, Lanzillo discloses a semiconductor device (100,500), comprising: metal lines 20 disposed in a metal level (see paragraphs [0064] and figs. 1-5); a dielectric barrier 30 conforming to a top and sides of the metal lines 20 (see paragraph [0072] and fig. 5); and a power plane 40 disposed over the dielectric barrier 30 and in-between the metal lines 20 (see paragraphs [0056], [0074] and fig. 5, note that element 40 being a metal such as copper, ruthenium, cobalt, tungsten which constitutes the power plane).
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In re claim 2, as applied to claim 1 above, Lanzillo discloses wherein the metal lines 20 include positively tapered shapes over which the dielectric barrier 30 conforms (see paragraphs [0073], [0074] and fig. 5).
In re claim 3, as applied to claim 1 above, Lanzillo discloses wherein the power plane 40 encapsulates the dielectric barrier 30 on three sides of the metal lines 20 (see paragraph [0074] and fig. 5, note that the power plane 40 located above the dielectric barrier 30 and cover the side surfaces and the top surface of the metal lines 20, see fig. 5).
In re claim 4, as applied to claim 1 above, Lanzillo discloses wherein the dielectric barrier 30 includes a hard mask portion on tops of the metal lines 30 (see paragraph [0074] and fig. 5).
In re claim 5, as applied to claim 1 above, Lanzillo discloses wherein the power plane (14,40) includes vias disposed between the metal lines (12,20) and connected to a device region 11 (see paragraphs [0056], [0074] and figs. 1-5).
In re claim 7, as applied to claim 1 above, Lanzillo discloses wherein the metal lines 20 and the power plane 40 are included in a power distribution network (see paragraph [0078] and figs. 5-7).
In re claim 8, as applied to claim 7 above, Lanzillo discloses wherein the power distribution network is included on a backside of the semiconductor device (see paragraph [0078] and figs. 5-7, note that, the power delivery network being a backside power delivery network).
In re claim 9, Lanzillo discloses a semiconductor device (100,500), comprising: a device region 11 including front end of the line (FEOL) devices (i.e., semiconductor devices) (see paragraphs [0060], [0094] and figs. 1-5), the device region 11 defining a frontside and a backside opposite the frontside of the semiconductor device; metal lines (12,20) disposed in a metal level on the backside (see paragraphs [0061], [0067] and figs. 1-5); a dielectric barrier (13,30) conforming to a top and sides of the metal lines (see paragraphs [0055], [0074] and figs. 1-5); and a power plane (14,40) disposed over the dielectric barrier (13,30), the power plane 40 extending to a region in-between the metal lines 20 to surround the metal lines 20 on three sides of the metal lines 20 (see paragraphs [0056], [0074] and figs. 1-5, note that, element 40 being a metal such as copper, ruthenium, cobalt, tungsten that constitutes the power plane, and the power plane 40 covers the side surfaces and the top surface of the metal lines 20, see fig. 5).
In re claim 10, as applied to claim 9 above, Lanzillo discloses wherein the metal lines (12,20) include positively tapered shapes over which the dielectric barrier (13,30) conforms (see paragraphs [0055], [0061], [0067], [0074] and figs. 1-5).
In re claim 11, as applied to claim 9 above, Lanzillo discloses wherein the dielectric barrier (13,30) includes a hard mask portion on tops of the metal lines (12,20) (see paragraphs [0055], [0061], [0067], [0074] and figs. 1-5).
In re claim 12, as applied to claim 9 above, Lanzillo discloses wherein the power plane (14,40) includes vias disposed between the metal lines (12,20) and connected to the device region 11 (see paragraphs [0056], [0074] and figs. 1-5).
In re claim 14, as applied to claim 9 above, Lanzillo discloses wherein the metal lines (12,20) and the power plane (14,40) are included in a backside power distribution network (see paragraph [0078 and figs. 1-7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15-17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lanzillo et al. (U.S. Pub. 2022/0406717) in view of Rubin et al. (U.S. Pub. 2020/0135645).
In re claim 15, Lanzillo discloses a semiconductor device (100,500), comprising: a device region 11 including front end of the line (FEOL) devices (semiconductor devices) (see paragraphs [0060], [0094] and figs. 1-5), the device region defining a frontside and a backside opposite the frontside of the semiconductor device; positively tapered metal lines (12,20) disposed in a metal level on the backside (see paragraphs [0061], [0067] and figs. 1-5); a dielectric barrier (13,30) conforming to three sides of the positively tapered metal lines (12,20) (see paragraphs [0055], [0074] and figs. 1-5, note that, the dielectric barrier (13,30) covers the side surfaces and the top surface of the metal liners (12,20)); and a power plane (14,40) disposed over the dielectric barrier (13,30) on the three sides of the positively tapered metal lines (12,20), the power plane (14,40) extending to a region in-between the positively tapered metal lines (12,20) (see paragraphs [0056], [0074] and figs. 1-5).
However, Lanzillo is silent to wherein the positively tapered metal lines are associated with a first supply voltage and the power plane is associated with a second supply voltage different from the first supply voltage.
However, Rubin discloses in a same field of endeavor, a semiconductor device, including, inter-alia, wherein the positively tapered metal lines are associated with a first supply voltage (VDD) (see paragraphs [0057], [0058] and fig. 1) and the power plane is associated with a second supply voltage (VSS) (see paragraph [0045] and fig. 1) different from the first supply voltage.
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Rubin into the semiconductor of Lanzillo in order to enable wherein the positively tapered metal lines are associated with a first supply voltage and the power plane is associated with a second supply voltage different from the first supply voltage to be realized in order to distribute positive and negative power supply voltage to the semiconductor devices (see paragraph [0005] of Rubin). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 16, as applied to claim 15 above, Lanzillo in combination with Rubin discloses wherein the dielectric barrier (13,30) includes a hard mask portion on tops of the positively tapered metal lines (12,20) (see paragraphs [0055], [0061], [0067], [0074] and figs. 1-5 of Lanzillo).
In re claim 17, as applied to claim 15 above, Lanzillo in combination with Rubin discloses wherein the power plane (14,40) includes vias disposed between the positively tapered metal lines (12,20) and connected to the device region 11 (see paragraphs [0056], [0074] and figs. 1-5 of Lanzillo).
In re claim 19, as applied to claim 15 above, Lanzillo in combination with Rubin discloses wherein the positively tapered metal lines (12,20) and the power plane (14,40) are included in a backside power distribution network (see paragraph [0078] and figs. 1-7 of Lanzillo).
In re claim 20, as applied to claim 15, Lanzillo in combination with Rubin discloses wherein the first supply voltage includes a positive supply voltage (see paragraphs [0057], [0058] of Rubin).
Claim(s) 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lanzillo et al. (U.S. Pub. 2022/0406717), as applied to claims 1 and 9 above, respective, and further in view of Kwon et al. (U.S. Pub. 2010/0156523).
In re claims 6 and 13, as applied to claims 1 and 9 above, respectively, Lanzillo is silent to wherein the semiconductor device further comprising a via connecting to one of the metal lines that passes through the power plane.
However, Kwon discloses in a same field of endeavor, a semiconductor device 200, including, inter-alia, a via connecting to one of the metal lines (210,220) that passes through the power plane 265 (see paragraph [0039] and fig. 2).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Kwon into the semiconductor device of Lanzillo in order to enable the semiconductor device to further comprising a via connecting to one of the metal lines that passes through the power plane in Lanzillo to be formed in order to stably supply a power to the semiconductor devices (see paragraph [0002] of Kwon).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lanzillo et al. (U.S. Pub. 2022/0406717) in view of Rubin et al. (U.S. Pub. 2020/0135645), as applied to claim 15 above, and further in view of Kown et al. (U.S. Pub. 2010/0156523).
In re claim 18, as applied to claim 15 above, Lanzillo and Rubin are silent to wherein the semiconductor device further comprising a via connecting to one of the positively tapered metal lines that passes through the power plane.
However, Kwon discloses in a same field of endeavor, a semiconductor device 200, including, inter-alia, a via connecting to one of the metal lines (210,220) that passes through the power plane 265 (see paragraph [0039] and fig. 2).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Kwon into the semiconductor device of Lanzillo in order to enable the semiconductor device to further comprising a via connecting to one of the positively tapered metal lines that passes through the power plane in Lanzillo to be formed in order to stably supply a power to the semiconductor devices (see paragraph [0002] of Kwon).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. (U.S. Pub. 2008/0080112) discloses a semiconductor device, including, inter-alia, metal lines 6190 disposed in a metal level and a power plane 811 disposed over the metal lines 6190 (see paragraph [0112] and fig. 3B).
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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