Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/15/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 26-45 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-20 of U.S. Patent No. 12,016,186 to Kim (hereinafter Kim). Although the claims at issue are not identical, they are not patentably distinct from each other because the change in claim language amounts to a rewording of the claim language already protected by Kim. Below, the pending claims are compared to their equivalent in the cited patent. The patented claim language is italicized.
Pending Claims 26 recites a semiconductor memory device, comprising:
first conductive lines provided on a substrate and extending in a first direction in parallel, the first direction being parallel to a top surface of the substrate; and
Patented Claim 1 recites a semiconductor memory device, comprising:
first conductive lines provided on a substrate and extending in a first direction in parallel, each of the first conductive lines including a first end portion and a second end portion that are opposite to each other, the first direction being parallel to a top surface of the substrate;
first selection transistors and second selection transistors respectively connected to the first conductive lines, wherein:
first selection transistors respectively connected to the first end portions of the first conductive lines; and
second selection transistors respectively connected to the second end portions of the first conductive lines, wherein:
each of the first selection transistors has a first gate width, and
each of the second selection transistors has a second gate width that is different from the first gate width.
each of the first selection transistors has a first gate width, and
each of the second selection transistors has a second gate width smaller than the first gate width.
Beyond a rewording of the already protect claim limitations, the difference in claims amounts to the pending application requiring the second gate width be different from the first gate width. The patented claim limitations require the second gate width be smaller than the first gate width. For the gate widths to be different, the second gate width must be either smaller or larger. If it’s smaller, the cited patent already protects the embodiment. If it’s larger, than it would have been obvious to form based on the cited patent since the gate width would have had predictable results based off the knowledge of the cited patent. Additionally, there does not appear to be support in the pending application for the second gate width to be larger than the first gate width. While the specification does mention the second gate width being different than the first, the only example of widths given is one in which the second gate width is smaller than the first gate width. Given these reasons, Examiner finds the pending claim language to be not patentably distinct from the cited patent.
For brevity, the dependent claims are matched to their equivalent in the cited patent without repetition of the claim language.
Pending Claim 27 is unpatentable in view of patented Claim 2.
Pending Claim 28 is unpatentable in view of patented Claim 3.
Pending Claim 29 is unpatentable in view of patented Claim 4.
Pending Claim 30 is unpatentable in view of patented Claim 5.
Pending Claim 31 is unpatentable in view of patented Claim 6.
Pending Claim 32 is unpatentable in view of patented Claim 7.
Pending Claim 33 is unpatentable in view of patented Claim 8.
Pending Claim 34 is unpatentable in view of patented Claim 9.
Pending Claim 35 is unpatentable in view of patented Claim 10.
Pending Claim 36 is unpatentable in view of patented Claim 11.
Pending Claim 37 is unpatentable in view of patented Claim 13.
Pending Claim 38 is unpatentable in view of patented Claim 14.
Pending Claim 39 is unpatentable in view of patented Claim 15.
Pending Claim 40 recites a semiconductor memory device, comprising:
a cell array portion disposed on a peripheral circuit portion, wherein:
the cell array portion includes:
first conductive lines, which extend in a first direction and are spaced apart from each other in a second direction crossing the first direction;
Patented Claim 19 recites a semiconductor memory device, comprising:
a cell array portion disposed on a peripheral circuit portion, wherein:
the cell array portion includes:
first conductive lines, which extend in a first direction and are spaced apart from each other in a second direction crossing the first direction;
second conductive lines, which are provided on the first conductive lines and extend in the second direction and are spaced apart from each other in the first direction; and
second conductive lines, which are provided on the first conductive lines and extend in the second direction and are spaced apart from each other in the first direction; and
memory cells respectively disposed between the first conductive lines and the second conductive lines,
the peripheral circuit portion includes:
memory cells respectively disposed between the first conductive lines and the second conductive lines,
the peripheral circuit portion includes:
first selection transistors, which are disposed on a first selection region on a substrate and are connected to the first conductive lines; and
second selection transistors, which are disposed on a second selection region on the substrate and are connected to the second conductive lines,
first selection transistors, which are disposed on a substrate and are connected to the first conductive lines; and
second selection transistors, which are disposed on the substrate and are connected to the second conductive lines,
an area of the first selection region is different from an area of the second selection region.
each of the first selection transistors has a first gate width, and each of the second selection transistors has a second gate width that is different from the first gate width.
Beyond a rewording of the already protect claim limitations, the difference in claims amounts to the pending application requiring the second gate width be different from the first gate width. However, a difference in gate widths would have necessarily required the selection regions be different in area to accommodate differing gate widths. Absent any other limitations beyond gate widths that would alter the selection regions, Examiner finds the pending claim to not be patentably distinct from the already patented claim language.
For brevity, the dependent claims are matched to their equivalent in the cited patent without repetition of the claim language.
Pending Claim 41 is unpatentable in view of patented Claim 19.
Pending Claim 42 is obvious in view of patented Claim 4.
Pending Claim 43 is obvious in view of patented Claims 11 & 16.
Pending Claim 44 is obvious in view of patented Claim 20.
Pending Claim 45 is unpatentable in view of patented Claim 18.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 26, 27, 40 and 41 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2018/0294277 to Kim et al (hereinafter Kim).
Regarding Claim 26, Kim discloses a semiconductor memory device, comprising:
first conductive lines (Fig. 11, BS) provided on a substrate and extending in a first direction in parallel, the first direction being parallel to a top surface of the substrate; and
first selection transistors (SPT1) and second selection transistors (SPT2) respectively connected to the first conductive lines, wherein:
each of the first selection transistors has a first gate width (A), and
each of the second selection transistors has a second gate width (B) that is different from the first gate width.
Regarding Claim 27, Kim discloses the device as claimed in claim 26, wherein:
the substrate includes a first selection region, in which the first selection transistors are disposed, and a second selection region, in which the second selection transistors are disposed (Fig. 11), and
an area of the first selection region is larger than an area of the second selection region (Fig. 11).
Regarding Claim 40, Kim discloses a semiconductor memory device, comprising:
a cell array portion disposed on a peripheral circuit portion (Fig. 11), wherein:
the cell array portion includes:
first conductive lines (Fig. 11), which extend in a first direction and are spaced apart from each other in a second direction crossing the first direction;
second conductive lines (Fig. 11), which are provided on the first conductive lines and extend in the second direction and are spaced apart from each other in the first direction; and
memory cells (Figs. 9 & 11) respectively disposed between the first conductive lines and the second conductive lines,
the peripheral circuit portion includes:
first selection transistors (SPT1), which are disposed on a first selection region on a substrate and are connected to the first conductive lines; and
second selection transistors (SPT2), which are disposed on a second selection region on the substrate and are connected to the second conductive lines,
an area of the first selection region is different from an area of the second selection region (Fig. 11).
Regarding Claim 41, Kim discloses the device as claimed in Claim 40, wherein:
each of the first selection transistors has a first gate width (A), and
each of the second selection transistors has a second gate width (B) that is different from the first gate width.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893