CTNF 18/665,082 CTNF 82021 DETAILED ACTION Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-10 and 15-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kim et al. (Kim, US 2022/0051972 A1) . Regarding claim 1, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2) including a first surface and a second surface opposite thereto (top surface and bottom surface of glass substrate 21), and including a plurality of through holes (core holes via 23) extending from the second surface to the first surface of the glass substrate (glass substrate 21); a plurality of wiring patterns ([0212]) each including a through electrode positioned in the plurality of through holes ( electrode located on top of through hole 21 as shown in FIG. 2) and a via pad extending from the through electrode to cover a portion of the second surface of the glass substrate (glass substrate 21); and a seed layer arranged between the glass substrate and the plurality of wiring patterns, and including a first surface coplanar with the first surface of the glass substrate (glass substrate 21), wherein the through electrode of each of the plurality of wiring patterns comprises a first surface coplanar ( see FIG. 1 at least practically) with the first surface of the glass substrate ( glass substrate 21). Regarding claim 2, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein the glass substrate ( glass substrate 21) comprises sidewalls defining the plurality of through holes ( sidewall of hole 21), and wherein the seed layer comprises a first portion between the second surface of the glass substrate and the via pad, and a second portion that extends from the first portion to the first surface of the glass substrate along the sidewalls of the glass substrate (glass substrate 21 see FIG. 1). Regarding claim 3, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein a side surface of the first portion of the seed layer is coplanar with a side surface of the via pad of each of the plurality of wiring patterns (see FIG. 1 i.e. at least part of it). Regarding claim 4, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein the seed layer extends conformally along a portion of the second surface of the glass substrate (glass substrate 21) and sidewalls of the glass substrate defining each of the plurality of through holes (see FIG. 1). Regarding claim 5, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein a horizontal width of each of the plurality of through holes ( hole 21) of the glass substrate (glass substrate 21) decreases (as shown in FIG. 2) toward the first surface of the glass substrate. Regarding claim 6, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein a horizontal width of the via pad of each of the plurality of wiring patterns ( at least bottom electrode pattern in FIG. 2) is greater than a horizontal width of each of the plurality of through holes ( hole 21). Regarding claim 7, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein a redistribution structure including a plurality of first redistribution vias ( wiring patter on both side of glass substrate 21) on the first surface of the glass substrate; and a plurality of external connection terminals on the via pad of each of the plurality of wiring patterns ( see FIG. 1), and disposed apart from the glass substrate in a vertical direction, wherein some of the plurality of the first redistribution vias of the redistribution structure contact the first surface of the through electrode of each of the plurality of wiring patterns, and a redistribution insulating layer of the redistribution structure covers a portion of the first surface of the through electrode and the first surface of the seed layer (see FIG. 2). Regarding claim 8, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein a redistribution structure on the second surface of the glass substrate; and a plurality of external connection terminals covering a portion of the first surface of the glass substrate, the first surface of the seed layer, and the first surface of the through electrode of each of the plurality of wiring patterns (see FIG. 1). Regarding claim 9, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein a first redistribution structure including a plurality of first redistribution vias on the first surface of the glass substrate; and a second redistribution structure including a plurality of second redistribution vias on the second surface of the glass substrate (see FIG. 1). Regarding claim 10, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein some of the plurality of first redistribution vias of the first redistribution structure contact the first surface of the through electrode of each of the plurality of wiring patterns (see FIG. 1). Regarding claim 15, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), and at least one semiconductor chip arranged on the package substrate, wherein the package substrate comprises: a glass substrate including a first surface and a second surface opposite thereto, and including a plurality of through holes extending from the second surface to the first surface of the glass substrate; a plurality of wiring patterns respectively positioned in the plurality of through holes, the plurality of wiring patterns each including a through electrode comprising a first surface coplanar with the first surface of the glass substrate and a via pad extending from the through electrode to cover a portion of the second surface of the glass substrate; a seed layer arranged between the glass substrate and the plurality of wiring patterns, and including a first surface coplanar with the first surface of the glass substrate; and a first redistribution structure arranged on at least one surface of the first surface and the second surface of the glass substrate, wherein the through electrode of each of the plurality of wiring patterns comprises a first surface coplanar with the first surface of the glass substrate (see FIG. 1 and related text). Regarding claim 16, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein the package substrate further comprises a second redistribution structure, wherein the second redistribution structure is arranged on a surface, on which the first redistribution structure is not arranged, among the first surface and the second surface of the glass substrate, and wherein a redistribution insulating layer of a redistribution structure arranged on the first surface of the glass substrate among the first redistribution structure and the second redistribution structure covers the first surface of the glass substrate, the first surface of the seed layer, and a portion of the first surface of the through electrode (see FIG. 2). Regarding claim 17, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein, when the first redistribution structure is arranged on the first surface of the glass substrate, a redistribution via of the first redistribution structure having a horizontal width less than a horizontal width of the through hole contacts each of the plurality of wiring patterns (see FIG. 2). Regarding claim 18, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein the package substrate comprises a cavity extending from the first surface of the glass substrate to the second surface of the glass substrate, and further comprises a buried semiconductor chip inside the cavity (see FIG. 1). Regarding claim 19, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), wherein the at least one semiconductor chip is mounted on the package substrate such that an active surface of the at least one semiconductor chip faces the package substrate, and the at least one semiconductor chip is electrically connected to the plurality of wiring patterns via the first redistribution structure (see FIG. 2). Regarding claim 20, Kim shows a package substrate comprising: a glass substrate (glass substrate 21 in FIG. 2), at least one semiconductor chip arranged on the package substrate; and an external connection terminal arranged on the package substrate, and disposed apart from the at least one semiconductor chip with the package substrate therebetween, wherein the package substrate comprises: a glass substrate including a first surface and a second surface opposite thereto, and including a plurality of through holes comprising a horizontal width decreasing and extending from the second surface to the first surface of the glass substrate; a plurality of wiring patterns respectively positioned in the plurality of through holes, the plurality of wiring patterns each including a through electrode comprising a first surface coplanar with the first surface of the glass substrate and a via pad extending from the through electrode to cover a portion of the second surface of the glass substrate; a seed layer arranged between the glass substrate and the wiring patterns, and including a first surface coplanar with the first surface of the glass substrate; a first redistribution structure including a plurality of redistribution vias, a redistribution insulating layer, and a plurality of redistribution line patterns, and arranged on the first surface of the glass substrate; and a second redistribution structure arranged on the second surface of the glass substrate, and including a plurality of redistribution vias, a redistribution insulating layer, and a plurality of redistribution line patterns, wherein the plurality of redistribution vias of the first redistribution structure have a horizontal width less than a horizontal width of each of the plurality of through holes, and contact the first surface of the through electrode of the plurality of wiring patterns (see FIG. 2) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893 Application/Control Number: 18/665,082 Page 2 Art Unit: 2893 Application/Control Number: 18/665,082 Page 3 Art Unit: 2893 Application/Control Number: 18/665,082 Page 4 Art Unit: 2893 Application/Control Number: 18/665,082 Page 5 Art Unit: 2893 Application/Control Number: 18/665,082 Page 6 Art Unit: 2893 Application/Control Number: 18/665,082 Page 7 Art Unit: 2893
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