DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 15 and 16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 15 recites the limitation “a length of each of the plurality of conductive posts in a vertical direction is equal to a length of each of the plurality of vertical connection conductors in the vertical direction”. This is not supported in the specification and is not illustrated in the drawings. Applicant’s “conductive post” is labeled 132/134. Applicant’s “vertical connection conductors” are labeled 172/174. If one looks at the drawings, these groups do not have equal vertical lengths. Elements 172/174 are far shorter than 132/134. Claim 16 is rejected for being dependent upon claim 15.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a length of each of the plurality of conductive posts in a vertical direction is equal to a length of each of the plurality of vertical connection conductors in the vertical direction” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al US 2020/0243449 and further in view of Rubin et al US 2021/0265275.
Pertaining to claim 1, Chiang teaches a semiconductor package comprising: a redistribution structure comprising:
a passivation layer 192 that is a single layer structure;
an under bump metallurgy (UBM) layer [0029] on a portion of a lower surface of the passivation layer; and
a conductive layer (conductive traces [0029]) in contact with the UBM layer and exposed from an upper surface of the passivation layer See Figure 1H opposite to the lower surface of the passivation layer;
a bridge chip 130 on the redistribution structure and comprising a bridge chip pad [0028] element 130b interfaces with conductive traces;
a first molding layer 154 sealing the bridge chip 130 on the redistribution structure 192;
a plurality of conductive posts 170 spaced apart from each other in a horizontal direction within the first molding layer 154, the bridge chip 130 being between the plurality of conductive posts see Figure 1H, and each of the plurality of conductive posts comprising a first surface and a second surface opposite to the first surface See Figure 1H; and
a plurality of semiconductor chips 111/121 on the first molding layer 154 and the bridge chip 130, each of the plurality of semiconductor chips comprising a chip pad 112a/112b and a solder bump,
wherein the first surface of each of the plurality of conductive posts 170 is bonded to the conductive layer (conductive traces in layer 192), and the second surface of each of the plurality of conductive posts 170 is bonded to a respective one of the plurality of semiconductor chips 111/121, and
Chiang fails to teach each of the plurality of semiconductor chips comprising a chip pad and a solder bump wherein the solder bump is configured to enable self-alignment between one conductive post from among the plurality of conductive posts and the chip pad.
Rubin teaches a bridge die 110 and semiconductor chips 140/150 comprising a chip pad and a solder bump 142/152, wherein the solder bump is configured to enable self-alignment (the solder bumps and the conductive posts of Rubin are aligned) between one conductive post 124/134 from among the plurality of conductive posts 124/134 and the chip pad See Figure 1E.
It would have been obvious to one of ordinary skill in the art at the time the invention as filed to replace the direct electrical bonding of the conductive elements as taught by Chiang with the solder bonding elements as taught by Rubin, since the two teach analogous art (bridge dies connecting two additional elements) and It would have been within the scope of one of ordinary skill because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed bonding step and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07. Direct bonding and solder bonding are interchangeable and based on design choice.
Product-By-Process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps.
“Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted) (Claim was directed to a novolac color developer. The process of making the developer was allowed. The difference between the inventive process and the prior art was the addition of metal oxide and carboxylic acid as separate ingredients instead of adding the more expensive pre-reacted metal carboxylate. The product-by-process claim was rejected because the end product, in both the prior art and the allowed process, ends up containing metal carboxylate. The fact that the metal carboxylate is not directly added, but is instead produced in-situ does not change the end product.).
Pertaining to claim 2, Chiang in view of Rubin teaches the semiconductor package of claim 1, wherein an upper surface of the conductive layer (conductive traces within 192) is in contact with the first surface of each of the plurality of conductive posts 170 See Chiang Figure 1H, and a lower surface of the conductive layer, opposite to the upper surface of the conductive layer, is in contact with the UBM layer 194 has UBM layer [0029] of Chiang.
Pertaining to claim 3, Chiang in view of Rubin teaches the semiconductor package of claim 1, wherein a center line passing through a center of the chip pad is located within 10 micrometers to 100 micrometers in the horizontal direction from a center line passing through a center of one of the plurality of conductive posts. Chiang teaches chip pads and conductive posts and the centerline of one of the pads 112a/112b is going to be within 10 to 100 micrometers of the center line of one of the conductive posts. We know this because Chiang teaches the scale of the device in at least [0034] where the bumps on the bridge die are 2 micrometers apart, extrapolating this out to the rest of the device shown in Figure 1H and the spacing of the conductive posts is going to be well within 100 micrometers thus the limitation of spacing is met given the breadth of the range. Regardless, spacing is an obvious design choice and appropriate spacing considerations would be made by one of ordinary skill in the art to account for both device size and function to ensure no electrical connections short or are otherwise unable to be manufactured with consistency based on spacing tolerances and material selection.
Pertaining to claim 4, Chiang in view of Rubin teaches the semiconductor package of claim 1, wherein the plurality of conductive posts each have a single cylindrical shape. Chiang teaches that the conductive posts are “pillars” [0025] and cylindrical shape is an obvious shape for a pillar. See In re Dailey, 149 USPQ 47 (CCPA 1976)
Appellants have presented no argument which convinces us that the particular configuration of their container is significant or is anything more than one of numerous configurations a person of ordinary skill in the art would find obvious for the purpose of providing mating. See Grahm v. John Deere Co., 383 U.S. l, 148 USPQ 459.
Pertaining to claim 5, Chiang in view of Rubin teaches the semiconductor package of claim 1, further comprising a second molding layer 154 on the first molding layer 150 and sealing the plurality of semiconductor chips 111/121, wherein an upper surface of the second molding layer and an upper surface of each of the plurality of semiconductor chips are on a same plane see Figure 1H of Chiang.
Pertaining to claim 6, Chiang in view of Rubin teaches the semiconductor package of claim 5, wherein the second molding layer comprises a same material as a material of the first molding layer [0025] Chiang.
Pertaining to claim 7, Chiang in view of Rubin teaches the semiconductor package of claim 1, wherein a length of each of the plurality of conductive posts 170 in a vertical direction is equal to a length of the first molding layer in the vertical direction see Figure 1H of Chiang.
Pertaining to claim 8, Chiang in view of Rubin teaches the semiconductor package of claim 1, wherein the plurality of semiconductor chips comprise a first semiconductor chip and a second semiconductor chip apart from the first semiconductor chip in the horizontal direction, and the first semiconductor chip comprises a logic semiconductor chip [0017], and the second semiconductor chip comprises a high bandwidth memory (HBM) chip Chiang [0006] teaches the use of the device with high bandwidth memory dies.
Pertaining to claim 9, Chiang in view of Rubin teaches the semiconductor package of claim 8, wherein the bridge chip is configured to provide an electrical connection path between the first semiconductor chip and the second semiconductor chip [0021] of Chiang.
Pertaining to claim 10, Chiang in view of Rubin teaches the semiconductor package of claim 1, further comprising an underfill material 180 on the first molding layer 150 and filling a space between the first molding layer 150 and the plurality of semiconductor chips 111/121, wherein the underfill material surrounds the chip pad and the solder bump It surrounds the chip pads and solder bumps connected to the bridge die and between both chips as illustrated in Figure 1H [0023] Chiang.
Pertaining to claim 12, Chiang teaches a semiconductor package comprising: a redistribution structure comprising:
a passivation layer 192 that is a single layer structure;
an under bump metallurgy (UBM) layer [0029] on a portion of a lower surface of the passivation layer; and
a conductive layer (conductive traces [0029]) in contact with the UBM layer and exposed from an upper surface of the passivation layer opposite to the lower surface of the passivation layer See Figure 1H;
a plurality of semiconductor chips 111/121 spaced apart on the redistribution structure in a horizontal direction;
a bridge chip 130 between the plurality of semiconductor chips and the redistribution structure and comprising a plurality of bridge chip pads [0028] element 130b interfaces with conductive traces;
a plurality of conductive posts 170 spaced apart from each other in the horizontal direction, the bridge chip being between the plurality of conductive posts and each of the plurality of conductive posts comprises a first surface bonded to the conductive layer See Figure 1H;
a plurality of vertical connection conductors between the plurality of semiconductor chips and the bridge chip, each of the plurality of vertical connection conductors comprising See Figure 1H marked up below:
a third surface bonded to a respective one of the plurality of bridge chip pads [0020]; and
a fourth surface bonded to a respective one of the second solder bumps [0020]; and
a first molding layer 154 disposed on the redistribution structure and sealing the bridge chip, the plurality of conductive posts, and the plurality of vertical connection conductors,.
PNG
media_image1.png
392
784
media_image1.png
Greyscale
Chiang fails to teach
a plurality of semiconductor chips spaced apart on the redistribution structure in a horizontal direction and each comprising chip pads, first solder bumps, and second solder bumps;
each of the plurality of conductive posts comprises a first surface bonded to the conductive layer and a second surface bonded to a respective one of the first solder bumps
wherein the first solder bumps are configured to enable self-alignment between the plurality of conductive posts and at least some of the chip pads
Rubin teaches a bridge die 110 and semiconductor chips 140/150 comprising a chip pad and a solder bump 142/152, wherein the solder bump is configured to enable self-alignment (the solder bumps and the conductive posts of Rubin are aligned) between one conductive post 124/134 from among the plurality of conductive posts 124/134 and the chip pad See Figure 1E.
It would have been obvious to one of ordinary skill in the art at the time the invention as filed to replace the direct electrical bonding of the conductive elements as taught by Chiang with the solder bonding elements as taught by Rubin, since the two teach analogous art (bridge dies connecting two additional elements) and It would have been within the scope of one of ordinary skill because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed bonding step and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07. Direct bonding and solder bonding are interchangeable and based on design choice.
Product-By-Process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps.
“Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted) (Claim was directed to a novolac color developer. The process of making the developer was allowed. The difference between the inventive process and the prior art was the addition of metal oxide and carboxylic acid as separate ingredients instead of adding the more expensive pre-reacted metal carboxylate. The product-by-process claim was rejected because the end product, in both the prior art and the allowed process, ends up containing metal carboxylate. The fact that the metal carboxylate is not directly added, but is instead produced in-situ does not change the end product.).
Pertaining to claim 13, Chiang in view of Rubin teaches the semiconductor package of claim 12, wherein the plurality of conductive posts overlap with the plurality of semiconductor chips in a vertical direction. See Chiang elements 170 and 111/121 and Figure 1H, the conductive posts clearly overlap with the chips
Pertaining to claim 14, Chiang in view of Rubin teaches the semiconductor package of claim 12, wherein the second surface of each of the plurality of conductive posts and the fourth surface of each of the plurality of vertical connection conductors are on a same plane. See Figure 1H marked up above, all of these are on the same plane.
Pertaining to claim 15, Chiang in view of Rubin teaches the semiconductor package of claim 12, wherein the plurality of conductive posts and the plurality of vertical connection conductors each have a single cylindrical shape, and a length of each of the plurality of conductive posts in a vertical direction is equal to a length of each of the plurality of vertical connection conductors in the vertical direction (the portion in italics is not supported in the specification or drawings see 112 rejection). Chiang teaches that the conductive posts are “pillars” [0025] and cylindrical shape is an obvious shape for a pillar. See In re Dailey, 149 USPQ 47 (CCPA 1976)
Appellants have presented no argument which convinces us that the particular configuration of their container is significant or is anything more than one of numerous configurations a person of ordinary skill in the art would find obvious for the purpose of providing mating. See Grahm v. John Deere Co., 383 U.S. l, 148 USPQ 459.
Pertaining to claim 16, Chiang in view of Rubin teaches the semiconductor package of claim 15, wherein a diameter of each of the plurality of conductive posts 170 is greater than a diameter of each of the plurality of vertical connection conductors See Figure 1H marked up above, the scale of the conductive posts in Chiang are larger than the scale of the conductive elements connecting the bridge die to the chips.
Pertaining to claim 17, Chiang in view of Rubin teaches the semiconductor package of claim 12, wherein a distance in the horizontal direction between a conductive post closest to a periphery of the bridge chip, among the plurality of conductive posts, and a vertical connection conductor closest to the periphery of the bridge chip, among the plurality of vertical connection conductors, is greater than a distance in the horizontal direction between a pair of conductive posts that are adjacent to each other among the plurality of conductive posts. See Figure 1H of Chiang, conductive posts 170 are closer together than 170 is to the vertical connection conductors (Figure 1H marked up above)
Pertaining to claim 18, Chiang in view of Rubin teaches the semiconductor package of claim 12, wherein a distance in the horizontal direction between a conductive post closest to a periphery of the bridge chip, among the plurality of conductive posts, and a vertical connection conductor closest to the periphery of the bridge chip, among the plurality of vertical connection conductors, is equal to a distance in the horizontal direction between a pair of conductive posts adjacent to each other among the plurality of conductive posts. This is taught by Rubin, post 124 is spaced roughly the same from element 136 as it is from adjacent 124. Even if not exactly equal: It would have been obvious to one of ordinary skill in the art at the time the invention was filed to space vias however one likes as long as they maintained function. The spacing is a design choice as required by size constraints, function constraints (will connections short out) and manufacturing constraints (can these be manufactured this close). When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the spacing/pitch of adjacent vias through routine experimentation and optimization to obtain optimal or desired device performance because the spacing is a result-effective variable (size/function/manufacturing requirements) and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
Pertaining to claim 19, Chiang/Rubin teaches a semiconductor package comprising:
a redistribution structure comprising:
a passivation layer that is a single layer structure;
an under bump metallurgy (UBM) layer on a portion of a lower surface of the passivation layer; and a conductive layer in contact with the UBM layer and exposed from an upper surface of the passivation layer opposite to the lower surface of the passivation layer;
a first semiconductor chip on the redistribution structure and comprising a first solder bump, a second solder bump, a first chip pad bonded to the first solder bump, and a second chip pad bonded to the second solder bump;
a second semiconductor chip on the redistribution structure, spaced apart from the first semiconductor chip in a horizontal direction, and comprising a third solder bump, a fourth solder bump, a third chip pad bonded to the third solder bump, and a fourth chip pad bonded to the fourth solder bump;
a bridge chip between the redistribution structure and the first semiconductor chip and comprising bridge chip pads and a bridge circuit electrically connected to the bridge chip pads, the bridge chip configured to provide an electrical connection path between the first semiconductor chip and the second semiconductor chip;
a first sealing layer sealing the bridge chip;
a first conductive post passing through the first sealing layer in a vertical direction on one side of the bridge chip; and
a second conductive post passing through the first sealing layer in the vertical direction on another side of the bridge chip opposite to the one side, wherein the first conductive post comprises a lower surface and an upper surface opposite to the lower surface of the first conductive post,
wherein the lower surface is bonded to the conductive layer and the upper surface is bonded to the first solder bump,
wherein the second conductive post comprises a lower surface and an upper surface opposite to the lower surface of the second conductive post,
wherein the lower surface is bonded to the conductive layer and the upper surface is bonded to the third solder bump,
wherein a horizontal distance between the second solder bump and the bridge chip is smaller than a horizontal distance between the first solder bump and the bridge chip See rejection of Claim 18,
wherein a horizontal distance between the fourth solder bump and the bridge chip is smaller than a horizontal distance between the third solder bump and the bridge chip See rejection of Claim 18,
wherein the first solder bump is configured to enable self-alignment between the first conductive post and the first chip pad See rejection of Claim 12, and
wherein the third solder bump is configured to enable self-alignment between the second conductive post and the second chip pad See rejection of Claim 12.
Claim 19 contains all the rejected subject matter found in claims 12-18 above under Chiang in view of Rubin. As such, Claim 19 is rejected in the same manner as above with the same motivation to combine as provided above.
Pertaining to claim 20, Chiang in view of Rubin teaches the semiconductor package of claim 19, further comprising:
a first vertical connection conductor passing through the first sealing layer in the vertical direction between the bridge chip and the first semiconductor chip; and
a second vertical connection conductor passing through the first sealing layer in the vertical direction between the bridge chip and the second semiconductor chip, wherein the first vertical connection conductor comprises a lower surface bonded to a first one of the bridge chip pads and an upper surface bonded to the second solder bump, and the second vertical connection conductor comprises a lower surface bonded to a second one of the bridge chip pads and an upper surface bonded to the fourth solder bump. See Chian figure 1H marked up below. See also Rubin Figure 1E elements 136 are bonded to the bridge pads and an upper surface to a solder bump 144.
PNG
media_image1.png
392
784
media_image1.png
Greyscale
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al US 2020/0243449 and further in view of Rubin et al US 2021/0265275.
Pertaining to claim 11, Chiang in view of Rubin teaches the semiconductor package of claim 1, including a bridge chip and a UBM pad on the lower surface of the passivation layer Chiang [0029], but fail to teach wherein the UBM layer comprises:
a UBM via, wherein a diameter of the UBM via decreases as a distance to the chip decreases.
Kwon teaches a UBM via wherein a diameter of the UBM via decreases as a distance to a chip 101 decreases See Figure 1 elements 104/105/107/108. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to select a via with a tapered shape as claimed, as the shape is known in the art for use as a via, in the claimed orientation, with UBM layers. It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Chiang and Kwon to enable the via step of Chiang to be performed according to the teachings of Kwon because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed via step of Chiang and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Appellants have presented no argument which convinces us that the particular configuration of their container is significant or is anything more than one of numerous configurations a person of ordinary skill in the art would find obvious for the purpose of providing mating. See Grahm v. John Deere Co., 383 U.S. l, 148 USPQ 459.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
Prosecution Insights