DETAILED ACTION
Claims 1-15 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The amended disclosure submitted on August 26, 2025, is objected to because of the following informalities:
In paragraph 4, line 4, replace “and then used for computations” does not fit grammatically in the sentence. The examiner recommends inserting a period after “data” in line 4 and then including a new sentence stating --The low-precision type data are then used for computations.--.
In paragraph 33, applicant did not underline the new equations, as required by 37 CFR 1.121. Please resubmit with underlining. The examiner also recommends submitting a substitute specification.
Appropriate correction is required.
Claim Recommendations
In claim 1, line 6, the examiner recommends either deleting “following” or replacing it with another word (e.g. “subsequent”) since there is a reference to “the following operations” in claim 5, but applicant is not referring back to the following operations of claim 1, but to the operations at the end of claim 5.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more.
Regarding step 1 of the Subject Matter Eligibility Test, claims 1-9 are directed to at least a machine, claims 10-12 are directed to a process, and claims 13-15 are directed to an article of manufacture
Regarding step 2A (prong 1) of the Subject Matter Eligibility Test, claim 1 recites executing an appointed arithmetic operation on a first operand and a second operand, wherein a precision of the first operand is different from a precision of the second operand. This step falls into the grouping of mathematical concepts (MPEP 2106.04(a)(2)). Such math would involve performing arithmetic like multiplication, addition, subtraction, or division (claim 4) on two different values with different precisions. For instance, one could add together a rounded integer such as 27 to a real (floating-point) number such as 34.5, to obtain a result of 61.5. Note that the second number is more precise since it includes a fractional portion whereas a rounded integer would not be as precise (its fractional portion would be lost). Thus, claim recites an abstract idea.
Regarding step 2A (prong 2) of the Subject Matter Eligibility Test, claim 1 recites the
following additional elements:
an instruction processing apparatus, comprising:
a register file comprising a plurality of registers;
a decoding unit including circuitry configured to: decode a mixed precision operation instruction; and acquire decoding information, the decoding information indicating an execution unit for executing following operations; and
an execution unit communicatively coupled to the register file and decoding unit and including circuitry configured to acquire the decoding information from the decoding unit for executing operations comprising:
the abstract idea identified above on a first register and a second register of the plurality of registers; and
writing an operation result back to a third register of the plurality of registers, the operands being of the first register and the second register.
These additional elements do not integrate the abstract idea into a practical application
because all elements except for the writing of the result to a third register amount to a mere instruction to apply the abstract idea in combination with a generic computer used as a tool to perform the abstract idea (see MPEP 2106.04(d)(I)), 6th bullet). The examiner notes that all claimed components are highly generic and found in all modern processors. Additionally, the writing step is insignificant post-solution activity that is incidental to the math calculation and that is no more than a nominal or tangential addition to the claim (see MPEP 2106.04(d)(I)), 7th bullet).
Regarding step 2B of the Subject Matter Eligibility Test, the additional elements, considered alone and in combination, do not amount to significantly more than the abstract idea because the courts have determined that using an instruction and a generic computer as a tool to perform the math does not amount to significantly more (see MPEP 2106.05(I)(A), second (i) and 2106.05(f)), and because writing a math operation result to storage (to a third register) has been deemed to be well-understood, routine, and conventional and not significantly more (see MPEP 2106.05(I)(A) and 2106.05(d), including section II, item (iv) (“storing…information in memory”)). Therefore, claim 1 is subject matter-ineligible.
Claim 2 is also ineligible because its additional elements constitute a generic instruction to perform the abstract idea. Therefore, these elements, alone or in combination with the others, do not integrate the abstract idea into a practical application, nor do they amount to significantly more (for similar reasoning given above).
Claim 3 recites additional elements of essentially not indicates a target register in the instruction, and the decoding unit determining the target instruction. The examiner asserts that this is insignificant extra solution activity that does not integrate the abstract ideas into a practical application. Additionally, it does not amount to significantly more because it is well-understood, routine, and conventional (i.e., typical) activity (see U.S. Patent No. 5,983,340, which states “A typical processor architecture may include a series of processing instructions where an instruction having an immediate data format can use one or more operands. Because immediate instructions can not specify all the operands they need, they use implied operands that are typically the result of the prior instruction. The typical implied operands are an "accumulator," a register usually located in the arithmetic unit of a processor, or a "top of stack," the last memory location used in a last in first out data memory mechanisms. In addition to an accumulator or top of stack a pipeline architecture has several pipeline latches or bus states that may contain useful data that could also be used as an implied operand.”). In other words, applicant is claiming extra-solution activity for a math operation that involves accumulation, where a generic instruction to perform the accumulation need not specify the accumulator as an operand. Instead, it is typical to imply it.
Claim 4 is also ineligible because it merely further defines the math operation to be performed.
Claim 5 is ineligible for similar reasoning as claim 1, with the claim reciting math to be performed (multiply-accumulation for multiplying values and adding a multiplication result to another value) and additional elements that amount to a mere instruction and generic computer to implement the abstract idea as well as the post-solution activity of writing the result of the math.
Claim 6 is ineligible because it amounts to generic registers in a generic computer to perform the math. In essence, the claim is reciting storing the result in a register than can accommodate the fractional portion of the input so as to not lose precision. For example, to add 27 and 34.5 and not lose the fractional part, the result register storage has to accommodate the fraction. A generic computer performs accurate math.
Claim 7 is ineligible because it merely recites more generic computer components (as well as a particular technological environment) that don’t integrate the math into a practical application or amount to significantly more.
Claim 8 is ineligible because it sets forth a generic RISC-V computer and thus the claim still only recites a generic computer as a tool to implement the math. Applicant may view the RISC-V Wikipedia page for an idea on how generic it is. Additionally, applicant is generally linking the abstract idea to a particular technological environment or field of use (RISC-V architecture). Such does not integrate the abstract idea into a practical applicant or amount to significantly more (MPEP 2106.04(d)(I), last bullet, and 2106.05(I)(A),
Claim 9 is ineligible because the claim merely sets forth that the generic instruction to implement the math is made part of a generic (RISC-V) instruction set. This is also a tie to a particular technological environment or field of use, which is not an integration into a practical application or significantly more.
Regarding step 2A (prong 1) of the Subject Matter Eligibility Test, claim 10 recites executing an appointed arithmetic operation on a first operand and a second operand, the first operand and the second operand being different precision values. For reasons set forth above for claim 1, this is a mathematical concept and, therefore, claim 10 recites an abstract idea.
Regarding step 2A (prong 2) of the Subject Matter Eligibility Test, claim 10 recites the
following additional elements:
reading the first operand to a first register indicated by the mixed precision operation from a first memory address;
reading the second operand to a second register indicated by the mixed precision operation from a second memory address;
executing the abstract idea on the first register and the second register by an execution unit indicated by the mixed precision operation, and storing an operation result to a third register indicated by the mixed precision operation; and
storing the operation result in the third register to a third memory address.
These additional elements do not integrate the abstract idea into a practical application
because the registers and memory addresses are generic computer components that are part of a generic computer used as a tool to perform the abstract idea (see MPEP 2106.04(d)(I)), 6th bullet), and the operation making various indications as to where data is stored and which execution unit is used amounts to use of a mere instruction (operation) to implement the abstract idea (see MPEP 2106.04(d)(I)), 6th bullet). Additionally, the reading, from memory, and storage, in registers, of data items on which the arithmetic is performed, as well as storing a result of the arithmetic in a register and memory are insignificant post-solution activity that are incidental to the math calculation and that is no more than nominal or tangential additions to the claim (see MPEP 2106.04(d)(I)), 7th bullet).
Regarding step 2B of the Subject Matter Eligibility Test, the additional elements, considered alone and in combination, do not amount to significantly more than the abstract idea because the courts have determined that using a generic computer as a tool and an instruction to perform the math does not amount to significantly more (see MPEP 2106.05(I)(A), second (i) and 2106.05(f)), and because reading and writing inputs and outputs from/to various storage components has been deemed well-understood, routine, and conventional activity and not significantly more (see MPEP 2106.05(I)(A) and 2106.05(d), including section II, items (i) and (iv) (“receiving or transmitting data over a network” (data gathering) and “storing and retrieving information in memory”)). Therefore, claim 10 is subject matter-ineligible.
Claim 11 is ineligible for similar reasoning as claim 6.
Claim 12 recites that each operation is performed by a generic assembly instruction, which, per the courts, does not integrate the math into a practical application, and does not amount to significantly more.
Claim 13 is ineligible, partly for similar reasoning as claim 10. Additionally, a generic medium and device to carry out the operations is part of generic instructions to perform the abstract idea on a generic computer used as tool to perform the idea. There is no integration into a practical application or significantly more.
Claim 14 is ineligible for similar reasoning as claim 6.
Claim 15 is not eligible for similar reasoning as claim 12.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Imel et al., U.S. Patent No. 4,823,260.
Referring to claim 1, Imel has taught an instruction processing apparatus, comprising:
a register file comprising a plurality of registers (see column 4, lines 17-32. There are a plurality of general registers (reg) and floating-point registers (fpr). Together, they collectively form a register file);
a decoding unit (FIG.1, decoder 12) including circuitry configured to:
decode a mixed precision operation instruction (see the instructions with CCC fields of 010, 100, 011, and 101 in column 4, lines 24-32. These instructions use both gen and fpr registers as sources and are referred to as mixed-precision instructions. Gen registers are 32-bit integer registers (e.g. see column 3, lines 1-5, and column 5, lines 64-65) while fpr registers are 80-bit registers (from column 4, lines 41-44, when fpr is used as a source, the data is loaded in extended precision, which means the data is 80 bits (see last line in column 4)); and
acquire decoding information, the decoding information indicating an execution unit for executing following operations (this is the purpose of the decoder. It obtains the various fields of the instructions so as to retrieve the appropriate data and generate the appropriate control signals to control the hardware to perform subsequent/following operations indicated by the instructions); and
an execution unit (e.g. FIG.2, 48) communicatively coupled to the register file (the execution unit obtains the data from the registers of the instructions in column 4 and is this coupled to the register file) and decoding unit (see FIG.1, where the decode (ID 12) is coupled to everything, including the execution unit inside FPU 22) and including circuitry configured to acquire the decoding information from the decoding unit for executing operations (again, this is how decoding/execution work) comprising:
executing an appointed arithmetic operation on a first register and a second register of the plurality of registers (taking the instruction having CCC = 011 as an example, the arithmetic operation indicated by fop is performed on the two registers (reg and fpr). The arithmetic operation may be any know floating-point operation, including addition (by the adder 56 in FIG.2). Divide is also given as an example in column 5, line 64, to column 6, line 46); and
writing an operation result back to a third register of the plurality of registers (from column 4, the instructions indicate a destination register. In the example of the instruction having CCC = 011, the destination/third register is an fpr register), wherein a precision of an operand of the first register is different from a precision of an operand of the second register (as described above, reg = 32 bits and fpr = 80 bits. Additionally, an integer in reg is a whole number with zero fractional precision, which a floating-point number in fpr has fractional precision).
Referring to claim 2, Imel has taught the instruction processing apparatus according to claim 1, wherein:
the mixed precision operation instruction comprises an operation code (column 4, e.g. instruction corresponding to CCC = 011, “fop” (opcode) field) and at least one operand (src1, src2, and dst fields in column 4); and
the at least one operand is used for indicating at least one of the first register (src1 indicates reg), the second register (src2 indicates fpr) and the third register (dst indicates fpr).
Referring to claim 4, Imel has taught the instruction processing apparatus according to claim 1, wherein the appointed arithmetic operation is multiplication (column 4, lines 49-52), addition (again, FPU includes an adder (FIG.2, 56), so the operation could be addition), subtraction, or division (as stated above, column 6 describes a division operation) (In general, it is understood that a FPU would perform all basic math operations).
Referring to claim 6, Imel has taught the instruction processing apparatus according to claim 1, wherein the precision indicated by the third register is the same as the higher precision in operands in the first register and the second register (again, see the CCC = 011 instruction in column 4. The inputs are 32 bits and 80 bits, and the third/destination register is another 80-bit register with extended precision), or higher than the higher precision in the operands in the first register and the second register.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Imel in view of San et al., U.S. Patent No. 5,724,497.
Referring to claim 3, Imel has taught the instruction processing apparatus according to claim 2, but has not taught wherein in response to the at least one operand not indicating the first register, the second register, and the third register simultaneously, the decoding unit includes circuitry configured to determine a target register that is not indicated in the at least one operand; and add a corresponding register identifier of the target register into the decoding information. However, San has taught that the destination register of an arithmetic instruction need not be explicitly specified by the instruction can be specified implicitly as a next sequential register of a source register (see column 16, lines 54-58). One of ordinary skill in the art would have recognized that an instruction can be reduced in size or include additional control if its dst field were eliminated or repurposed, respectively. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Imel such that a destination register is not explicitly indicated but is determined by the decoder and included as part of the decoding information so that the implied register is written with the result.
Claims 5 and 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over Imel in view of the examiner’s taking of Official Notice.
Referring to claim 5, Imel has taught the instruction processing apparatus according to claim 1, but has not taught wherein in response to the appointed arithmetic operation being multiply accumulation, the decoding unit includes circuitry configured to indicate the execution unit for executing the following operations: multiplying values stored in the first register and the second register; adding a multiplication result to a value stored in the third register; and writing an addition result back to the third register. However, such a multiply-accumulate process was well known in the art before applicant’s invention. Such an operation is prevalent in application such as filtering, matrix multiplication, dot product calculation, artificial intelligence, etc. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Imel such that, in response to the appointed arithmetic operation being multiply accumulation, the decoding unit includes circuitry configured to indicate the execution unit for executing the following operations: multiplying values stored in the first register and the second register; adding a multiplication result to a value stored in the third register; and writing an addition result back to the third register.
Referring to claim 8, Imel has taught the instruction processing apparatus according to claim 1, but has not taught wherein an instruction set architecture of the instruction processing apparatus is a RISC-V instruction set architecture. However, mixed-precision instructions could be useful in any architecture so as to add values of different data types/precisions. Official Notice is taken that the RISC-V ISA was well known in the art before applicant’s invention. RISC-V is an open source, extendable instruction set architecture whose base alone can implement a general-purpose computer and whose design is compact and deployable without royalties. Though not formally cited herein, applicant can view the Wikipedia entry for “RISC-V” for further information. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Imel’s system to be a RISC-V system whose base instruction set is extended to include the unique mixed-precision instructions of Imel.
Referring to claim 9, Imel, as modified, has taught the instruction processing apparatus according to claim 8, wherein the mixed precision operation instruction is an extended instruction of the RISC-V instruction set architecture (see the rejection of claim 8).
Claim 10 is partly rejected for similar reasoning as claim 1. Furthermore, while Imel has not taught reading a first operand to a first register indicated by the mixed precision operation from a first memory address; reading a second operand to a second register indicated by the mixed precision operation from a second memory address; and storing the operation result in the third register indicated by the mixed precision operation to a third memory address, Official Notice is taken that such operations correspond to LOAD and STORE operations that were well known in the art before applicant’s invention. STOREs support longer-term storage of data to free up the registers for current operations. LOADs perform the reverse and would be useful to bring data in from non-volatile storage such as hard disk. This to support longer-term storage and free up fast register storage, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Imel to load/read data from memory addressed into registers and stores registered results into memory at an address.
Claim 11 is rejected for similar reasoning as claim 6.
Referring to claim 12, Imel, as modified, has taught the processing method according to claim 10, wherein each operation of the processing method corresponds to an assembly instruction (as described above, assembly LOADS and STORES would be performed around the arithmetic assembly instruction (ADD, MULT, DIV, etc.).).
Claim 13 is mostly rejected for similar reasoning as claim 10. Furthermore, Imel has taught a non-transitory computer readable medium (column 2, lines 43-45; the memory and/or cache from which instructions are fetched), storing a set of instructions that are executable by one or more processors (FIG.1) to perform the claimed operations.
Claims 14-15 are rejected for similar reasoning as claims 6 and 12.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Imel.
Referring to claim 7, Imel has taught the instruction processing apparatus according to claim 1, but has not taught wherein the first register is an 8-bit integer register, and the second register is an 8-bit, 16-bit, 19-bit, 32-bit, or 64-bit floating-point register. Instead, Imel has taught the first register is a 32-bit integer register and the second register is an 80-bit floating-point register. However, changing sizes of the registers is a routine expedient, not a patentable distinction, particular absent a demonstration of the criticality of the specific sizes (see MPEP 2144.04, including section (IV)(A)). Any sizes could be used. In this case, reducing integer registers from 32 bits to 8 bits, and reducing 80-bit registers from 80 bits to one of the claimed sizes would reduce the hardware footprint (since registers would be smaller). This would also reduce power consumption since less data is being transferred through the system and operated on, resulting in fewer switching transistors. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Imel such that the first register is an 8-bit integer register, and the second register is an 8-bit, 16-bit, 19-bit, 32-bit, or 64-bit floating-point register.
Response to Arguments/Amendments
In section VII of applicant’s response (hereafter “the response”), applicant notes the removal of “device” from claim 13 and asks that 112(f) interpretation be withdrawn.
The examiner notes the removal such that structural processors now perform the operations of claim 13. As such, broadest reasonable interpretation, as opposed to 112(f) interpretation, now applies to claim 13.
In section VIII(A)(1) of the response, applicant argues that the examiner does not identify what the abstract idea is.
The examiner respectfully disagrees. The examiner pointed out the claim limitations, i.e., executing an appointed arithmetic operation first and second operands having different precision, and identified which abstract idea grouping such limitations fall into (mathematical concepts). The examiner even gave an example of a type of math that is encompassed by applicant’s claim 1 (e.g. addition of 27 to 34.5).
In section VIII(A)(2) of the response, applicant argues that the Office fails to indicate whether the claim as a whole integrates the abstract idea into a practical application.
The examiner respectfully disagrees. The examiner has analyzed all limitations of the claims. Thus, the claim has been considered as a whole. If the examiner had concluded that, as a whole, claim 1 integrated the abstract idea into a practical application, then the examiner would not have made a 101 rejection.
In section VIII(A)(2) of the response, on pp.19-20, applicant argues that the claims improve the functioning of a computer and therefore integrate any abstract idea into a practical application.
Per MPEP 2106.05(a), “the claim must be evaluated to ensure the claim itself reflects the disclosed improvement in technology. Intellectual Ventures I LLC v. Symantec Corp., 838 F.3d 1307, 1316, 120 USPQ2d 1353, 1359 (Fed. Cir. 2016) (patent owner argued that the claimed email filtering system improved technology by shrinking the protection gap and mooting the volume problem, but the court disagreed because the claims themselves did not have any limitations that addressed these issues). That is, the claim must include the components or steps of the invention that provide the improvement described in the specification.” The examiner asserts that any alleged improvement involving lack of operand conversion, not using temporary storage and conversion buffers, etc., are not reflected within the claim. Applicant’s claim merely covers using generic computer components and an instruction to perform math on values with different precisions. The claims even cover performing conversion, which is evidence that applicant’s alleged improvement is not reflected within the claims. Note that the examiner is not saying that claiming the improvement would overcome the 101. That would require further analysis. The examiner is merely saying that the current claims don’t reflect any improvement and thus they are not subject matter eligible under 101.
With respect to the argument in section VIII(B), the argument is not persuasive for reasoning given above. Applicant’s claims merely cover using generic computer components and an instruction to perform math, along with insignificant extra-solution activity that has been deemed to be well-understood, routine, and conventional by the courts. Thus, significantly more than the abstract idea is not claimed.
The argument in section IX(A) of the response, regarding Imel not teaching that the decoding information indicate an execution unit, is not persuasive. This is how processors work. A decoder reacts to an instruction opcode to enable a particular execution unit to carry out the operation indicated by the opcode. For instance, when an add instruction is decoded, an adder execution unit (e.g. FIG.2, adder(s) 56,60) would be controlled to performing addition. If a multiply or divide instruction were instead to be performed, the decode instruction would indicate a multiplier/divider execution unit is to be used. In general, different instruction opcodes activate different execution units to carry out the respective operations.
The argument in section IX(B) of the response, regarding Imel teaching away from mixed-precision operations, is not persuasive. The examiner is not clear on why applicant believes storing an 80-bit (extended) result teaches away from mixed precision operations. It is not the result that necessarily matters, but the inputs. For the four operations pointed out by the examiner in the rejection, one input is a 32-bit integer, and another is a floating-point value with more bits. These operations are referred to as “mixed precision” in column 4 of Imel. Thus, Imel actually teaches, not teaches away from, the claimed invention.
Conclusion
The following prior art previously made of record and not relied upon is considered pertinent to applicant's disclosure:
Poland, U.S. Patent No. 5,673,407, has taught arithmetic instructions that may operate on both single and double precision operands (see TABLE 1 in column 18). This document is deemed particularly relevant to applicant’s claims.
Ould-Ahmed-Vall, U.S. Patent Application Publication No. 2018/0315159, has taught a mixed-precision multiply-accumulate instruction that multiplies at least one 16-bit floating-point value and accumulates a 32-bit floating-point value.
Sun, U.S. Patent No. 6,675,286, has taught instructions in FIG.11 that operate on sources with different size/precision operands.
Reggiani has taught “Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices”, and extension of RISC-V with custom instructions.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183