Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on August 11, 2026, regarding the application filed May 15, 2024.
Election/Restrictions
Applicant’s election without traverse of Invention I, corresponding to claims 1-15, in the reply filed on August 11, 2026 is acknowledged. Claims 16-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. This restriction requirement has been finalized.
Claims 1-20 are pending, with claims 16-20 currently withdrawn from consideration.
Priority
Acknowledgment is made of Applicant's claim for foreign priority based Korean Patent Application No. 10-2023-0159575, filed on November 16, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 15, 2024 has been placed in the application file and is being considered by the examiner.
Drawings
The drawings filed with the application on May 15, 2024 are accepted.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 11 recites, inter alia, wherein the width of the lower surface of the first redistribution via and lower side portions of the first seed metal layer between the first redistribution via and the dielectric, in the horizontal direction is in a range from about 8 μm to about 10 μm. It is unclear whether the width refers to the total combined width of the lower surface of the first redistribution via and lower side portions of the first seed metal layer, or to the width of the lower surface of the first redistribution via being equal to the width of lower side portions of the first seed metal layer. For examination purposes, this limitation has been interpreted as: wherein the width of the lower surface . Support for this interpretation is provided, for example, at paragraph [0043] and in FIG. 2 of Applicant’s disclosure. This rejection may be overcome by amending claim 11 to particularly point out and distinctly claim the subject matter of the invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al., US 2021/0265296 A1 (hereinafter Choi) in view of Jeon et al., US 2021/0028137 A1 (hereinafter Jeon).
Regarding claim 1, Choi discloses: A semiconductor structure comprising: a first redistribution line (Choi, FIG. 9, second redistribution layer 142b, [0084; 0086]);
a first redistribution via on the first redistribution line (Choi, FIG. 9 shows second connection via 143b [the first redistribution via] on second redistribution layer 142b [the first redistribution line], [0087]), the first redistribution via having a width in a horizontal direction that decreases from a bottom end of the first redistribution via to a top end of the first redistribution via (Choi, FIG. 9 shows second connection via 143b [the first redistribution via] having a tapered shape narrower at the top than at the bottom, i.e., having a width in a horizontal direction that decreases from a bottom end to a top end, [0087]);
a second redistribution line on the first redistribution via (Choi, FIG. 9 shows first redistribution layer 142a [the second redistribution line] on second connection via 143b [the first redistribution via], [0087]);
a dielectric surrounding the first redistribution line, the first redistribution via, and the second redistribution line (Choi, FIG. 9 shows first insulating layer 141a [the dielectric] surrounding second redistribution layer 142b [the first redistribution line], second connection via 143b [the first redistribution via], and first redistribution layer 142a [the second redistribution line], [0068-0069]); and
a first seed metal layer
Although Choi teaches the use of a seed metal layer (Choi, metal seed layer formed during plating process, see [0088]), Choi is silent regarding: a first seed metal layer between a lower surface of the first redistribution via and the first redistribution line, between a side surface of the first redistribution via and the dielectric, and between a lower surface of the second redistribution line and the dielectric.
However, Jeon, in the same field of endeavor, teaches: a first seed metal layer between a lower surface of the first redistribution via and the first redistribution line (Jeon, FIGs. 1K-1N show second seed layer 121 [the first seed metal layer], between lower surface of second via part 120V [the first redistribution via] and first line parts 110W of the first redistribution patterns 110 [the first redistribution line], [0052-0053]), between a side surface of the first redistribution via and the dielectric (Jeon, FIGs. 1K-1N show second seed layer 121 [the first seed metal layer] between a side surface of second via part 120V [the first redistribution via] and third dielectric layer 103 [the dielectric]), and between a lower surface of the second redistribution line and the dielectric (Jeon, FIGs. 1K-1N show second seed layer 121 [the first seed metal layer] between a lower surface of second line parts 120W [the second redistribution line] and third dielectric layer 103 [the dielectric], [0044-0053]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Choi with the teachings of Jeon, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Jeon, to use the seed layer as an electrode during the electroplating process in order to form vias and redistribution patterns (Jeon, [0052]), thereby providing for device functionality.
Regarding claim 2, Choi in view of Jeon teaches: The semiconductor structure of claim 1, further comprising: a second redistribution via on the second redistribution line and in the dielectric (Choi, FIG. 9 shows first connection via 143a [the second redistribution via] on first redistribution layer 142a [the second redistribution line] and in first insulating layer 141a [the dielectric], [0068]), wherein the second redistribution via has a width in the horizontal direction that decreases from a bottom end of the second redistribution via to a top end of the second redistribution via (Choi, FIG. 9 shows first connection via 143a [the second redistribution via] has a width in the horizontal direction that decreases from a bottom end to a top end, [0087]).
Regarding claim 3, Choi in view of Jeon teaches: The semiconductor structure of claim 2, further comprising: a bonding pad on the second redistribution via (Choi, FIG. 9 shows connection pad 122 [the bonding pad] on the first connection via 143a [the second redistribution via], [0068]).
Regarding claim 4, Choi in view of Jeon teaches: The semiconductor structure of claim 3, further comprising: a second seed metal layer between a lower surface of the second redistribution via and the second redistribution line (Jeon, FIGs. 1K-1N show third seed layer 131 [the second seed metal layer], between lower surface of third via part 130V [the second redistribution via] and second line parts 120W of the second redistribution patterns 120 [the second redistribution line], [0052-0056]), between a side surface of the second redistribution via and the dielectric (Jeon, FIGs. 1K-1N show third seed layer 131 [the second seed metal layer] between a side surface of third via part 130V [the second redistribution via] and fourth dielectric layer 104 [the dielectric]), and between a lower surface of the bonding pad and the dielectric (Jeon, FIG. 1M shows third seed layer 131 [the second seed metal layer] between a lower surface of conductive pad 140 [the bonding pad] and third dielectric layer 103 [the dielectric], [0044-0058]).
Regarding claim 5, Choi in view of Jeon teaches: The semiconductor structure of claim 1, wherein the first redistribution via (Choi, FIG. 9, second connection via 143b [the first redistribution via]) and the second redistribution line (Choi, FIG. 9, first redistribution layer 142a [the second redistribution line]) have an integrated shape (Choi, FIG. 9 shows second connection via 143b [the first redistribution via] and first redistribution layer 142a [the second redistribution line] as an integral structure, i.e., having an integrated shape, resulting from being simultaneously formed using a plating process, [0088]).
Regarding claim 6, Choi in view of Jeon teaches: The semiconductor structure of claim 1, wherein the dielectric (Choi, FIG. 9, first insulating layer 141a) is a photoimageable dielectric (PID) (Choi, “first insulating layer 141a [the dielectric], commonly containing a photoimageable dielectric (PID) material,” [0069; 0085]).
Regarding claim 7, Choi in view of Jeon teaches: The semiconductor structure of claim 1, wherein the first seed metal layer continuously extends between the lower surface of the first redistribution via and the first redistribution line (Jeon, FIGs. 1K-1N show second seed layer 121 [the first seed metal layer], continuously extends between lower surface of second via part 120V [the first redistribution via] and first line parts 110W of the first redistribution patterns 110 [the first redistribution line], [0052-0053], between the side surface of the first redistribution via and the dielectric (Jeon, FIGs. 1K-1N show second seed layer 121 [the first seed metal layer] continuously extends between a side surface of second via part 120V [the first redistribution via] and third dielectric layer 103 [the dielectric]), and between the lower surface of the second redistribution line and the dielectric (Jeon, FIGs. 1K-1N show second seed layer 121 [the first seed metal layer] continuously extends between a lower surface of second line parts 120W [the second redistribution line] and third dielectric layer 103 [the dielectric], [0044-0053]).
Regarding claim 8, Choi in view of Jeon teaches: The semiconductor structure of claim 1, wherein a cross-sectional shape of the first redistribution via in the horizontal direction includes a trapezoid shape (Choi, FIG. 9 shows second connection via 143b [the first redistribution via] having a trapezoid shape), a circular shape, an oval shape, a rectangular shape, or a hexagonal shape.
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Choi include one or more of Applicant’s claimed alternative elements, for example: a trapezoid shape.
Regarding claim 9, Choi in view of Jeon teaches: The semiconductor structure of claim 1, wherein an area of the lower surface of the first redistribution via is larger than an area of an upper surface of the first redistribution via (Choi, FIG. 9 shows area of lower surface of second connection via 143b [the first redistribution via] is larger than area of upper surface of second connection via 143b [the first redistribution via], [0072]).
Regarding claim 10, Choi in view of Jeon teaches: The semiconductor structure of claim 1, wherein an angle between an upper surface of the first redistribution line and a side surface of the first seed metal layer is in a range from about 100° to about 110° (Jeon, see FIG. 1L, “second redistribution pattern 120 [shown coplanar with upper surface of first redistribution patterns 110, i.e., the upper surface of the first distribution line] may have an angle θ30 ranging from about 105° to about 135° between a bottom surface and a sidewall of the second via part 120V [the first redistribution via, shown conformally plated onto second seed layer 121 [the first seed metal layer]],” [0053]). The angle taught by Choi in view of Jeon is within Applicant’s claimed range.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Jeon and further in view of Yu et al., US 2020/0411469 A1 (hereinafter Yu).
Regarding claim 11, insofar as the claim can be understood in view of the 35 USC 112 rejections or claim objections above, Choi in view of Jeon teaches: The semiconductor structure of claim 1. Choi in view of Jeon is silent regarding: wherein the width of the lower surface
However, Yu, in the same field of endeavor, teaches: wherein the width of the lower surface of the first seed metal layer in the horizontal direction is in a range from about 8 μm to about 10 μm (Yu, FIG. 4B shows width W2 of lower surface of conductive layer 82 [analogous to the seed layer], “a width W2 of from about 1 μm to about 40 μm,” [0034-0038]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Choi in view of Jeon with the teachings of Yu, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Yu, to provide metallization patterns for electrical interconnection (Yu, [0035]), thereby providing for device functionality.
Regarding claim 12, Choi in view of Jeon and further in view of Yu teaches: The semiconductor structure of claim 1, wherein a height from the lowermost surface of the first seed metal layer (Yu, FIG. 4B, lowermost surface of conductive layer 82, [0037]) to an upper surface of the first redistribution via in a vertical direction (Yu, FIG. 4B, upper surface of reflowable layer 84, [0037]) is in a range from about 3 μm to about 3.5 μm (Yu, FIG. 4B shows thickness T3 from lower surface of conductive layer 82 [analogous to the seed layer] to upper surface of reflowable layer 84 [analogous to the upper surface of the first redistribution via] of about 1 μm to about 5 μm, [0034-0038]).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Jeon and further in view of Marcoux, US 2011/0079912 A1 (hereinafter Marcoux.
Regarding claim 13, Choi discloses: A semiconductor chip comprising: a substrate including a front side and a back side opposite to the front side (Choi, FIG. 9, body 121 [the substrate] of semiconductor chip 120 [the semiconductor chip], shown as a rectangular structure having an upper surface [the front side] and a lower surface [the back side] opposite to the front side, [0080]);
an active layer (Choi, FIG. 9, active surface (not shown), [0068])
a back side redistribution structure on the back side of the substrate (Choi, FIG. 9, connection structure 140 [the redistribution structure] shown on bottom side [the back side] of body 121 [the substrate]),
wherein the back side redistribution structure includes: a plurality of first redistribution lines (Choi, FIG. 9, second redistribution layers 142b, [0084; 0086]);
a plurality of redistribution vias on the plurality of first redistribution lines (Choi, FIG. 9 shows second connection vias 143b [the first redistribution vias] on second redistribution layers 142b [the first redistribution lines], [0087]), each of plurality of redistribution vias having a width in a horizontal direction that decreases from a bottom end of each of the plurality of redistribution vias to a top end of each of the plurality of redistribution vias (Choi, FIG. 9 shows each of second connection vias 143b [the first redistribution vias] having a tapered shape narrower at the top than at the bottom, i.e., having a width in a horizontal direction that decreases from a bottom end to a top end, [0087]);
a plurality of second redistribution lines on the plurality of redistribution vias (Choi, FIG. 9 shows first redistribution layers 142a [the second redistribution lines] on second connection vias 143b [the first redistribution vias], [0087]);
a dielectric surrounding the plurality of first redistribution lines, the plurality of redistribution vias, and the plurality of second redistribution lines (Choi, FIG. 9 shows first insulating layer 141a [the dielectric] surrounding second redistribution layers 142b [the first redistribution lines], second connection vias 143b [the first redistribution vias], and first redistribution layers 142a [the second redistribution lines], [0068-0069]);
Although Choi teaches a substrate including an active layer, Choi is silent regarding: an active layer on the front side the active layer including an integrated circuit structure; a wiring layer on the active layer.
However, Marcoux, in the same field of endeavor, teaches: an active layer on the front side (Marcoux, FIGs. 2 and 3 show active surface 36 [the active layer] on upper surface [the front side] of chip 22, [0033]) the active layer including an integrated circuit structure (Marcoux, “the circuit [the integrated circuit structure] is located at one surface or side of the chip, also called the active surface, front side, or top side,” [0032]); a wiring layer on the active layer (Marcoux, FIGs. 2 and 3 show contact trace 46 [the wiring layer] on active surface 36 [the active layer], [0034-0035]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Choi with the teachings of Marcoux, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Marcoux, to provide an electrical connection extending from the circuit side of a chip to its back side, and connecting to traces on the circuit (Marcoux, [0034]), thereby providing for device functionality.
Although Choi teaches the use of a seed metal layer (Choi, metal seed layer formed during plating process, see [0088]), Choi is silent regarding: a plurality of seed metal layers disposed between lower surfaces of the plurality of redistribution vias and the plurality of first redistribution lines, between side surfaces of the plurality of redistribution vias and the dielectric; and between the dielectric and lower surfaces of the plurality of second redistribution lines.
However, Jeon, in the same field of endeavor, teaches: a plurality of seed metal layers disposed between lower surfaces of the plurality of redistribution vias and the plurality of first redistribution lines (Jeon, FIGs. 1K-1N show second seed layers 121 [the plurality of seed metal layers], between lower surfaces of second via parts 120V [the plurality of first redistribution vias] and first line parts 110W of the first redistribution patterns 110 [the plurality of first redistribution lines], [0052-0053]), between side surfaces of the plurality of redistribution vias and the dielectric (Jeon, FIGs. 1K-1N show second seed layers 121 [the plurality of seed metal layers] between side surfaces of second via parts 120V [the plurality of first redistribution vias] and third dielectric layer 103 [the dielectric]), and between the dielectric and lower surfaces of the plurality of second redistribution lines (Jeon, FIGs. 1K-1N show second seed layers 121 [the plurality of seed metal layers] between third dielectric layer 103 [the dielectric] and lower surfaces of second line parts 120W [the plurality of second redistribution lines], [0044-0053]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Choi and Marcoux with the teachings of Jeon, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Jeon, to use the seed layer as an electrode during the electroplating process in order to form vias and redistribution patterns (Jeon, [0052]), thereby providing for device functionality.
Regarding claim 14, Choi in view of Marcoux and further in view of Jeon teaches: The semiconductor chip of claim 13, further comprising: a plurality of through silicon vias that extends from the front side to the back side of the substrate (Marcoux, FIGs. 2 and 3 show TSV connector 48 [the through silicon vias] extends from the upper surface [the front side] to the lower surface [the back side] of chip 22 [the substrate], “TSVs can be formed also at optimum locations within the active circuit areas,” [0034-0035]).
Regarding claim 15, Choi in view of Marcoux and further in view of Jeon teaches: The semiconductor chip of claim 14, wherein the plurality of through silicon vias (Marcoux, FIG. 3, TSV connector 48) are electrically connected to the back side redistribution structure (Marcoux, FIGs. 2 and 3 show TSV connector 48 [the through silicon vias] extends from the upper surface [the front side] to the lower surface [the back side] of chip 22 [the substrate] and is electrically connected to chip carrier substrate 26 [the back side redistribution structure], [0030; 0034-0035]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. The cited prior art discloses similar materials, devices, and methods.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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