DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to applicant’s communication filed 1/26/2026 in response to PTO Office Action mailed 12/10/2025. The applicant’s remarks and amendments to the claims and/or specification were considered with the results that follow.
In response to last Office Action, claims 4, 13 and 18 have been amended. No claims have been canceled. No claims have been added. As a result, claims 1-20 remain pending in this application.
The objection(s) and/or rejection(s) not repeated in this Office Action, have been withdrawn due to the amendment(s) and/or remarks filed on 1/26/2026.
Response to Arguments
Applicant's arguments filed 1/26/2026 have been fully considered but they are not persuasive.
The Applicant argues that Swaine does not disclose that GPU sends an address translation request containing the first physical address to the SMMU and receives an address translation response back from the SMMU. The Examiner respectfully disagrees with the fact. As admitted by the Applicant, Swaine teaches that the GPU may use multi-stage address translation process, where MMU performs the stage one translation, where virtual address is translated into an intermediate physical address and the SMMU then be used to perform stage two address translation. Here, it is noted that although it is not explicitly disclosed that the instructions are transmitted between various components such as MMU and SMMU, it is inherent that the instructions must be provided to each component of the computer system for them work as intended. Therefore, as noted, when Swaine discloses that the system translates the address using MMU and SMMU, both the components must be instructed for the operations to be performed.
The applicant also argues that Swaine does not disclose that the SMMU operates as a second translation agent associated with the CPU and services translation requests initiated by an I/O device as recited in the claims. The Examiner again respectfully disagrees with the fact. First it is noted that, according to MPEP § 2111, the Examiner must give the claimed terms, broadest reasonable interpretation. Swaine fig. 11, shows that MMU 610, 630 and SMMU 625 each connected to each other and communicates with each other. It is also noted that the term “associated with” is interpreted as the CPUs and GPU each communicate with the SMMU and therefore, it can be interpreted as associated with any component of the system.
Thus, the Applicant’s arguments are not persuasive and therefore the rejection of the claims is maintained and reiterated below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4, 10, 12-13 and 19 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Swaine et al. (US 2024/0045802).
As per claims 1, 10 and 19, Swaine teaches a system (Swaine: par. [0102])/method (Swaine: claim 19)/one or more processors (Swaine: fig. 11, items 600, 615, 620) comprising:
a central processing unit (CPU); and a first input/output (I/O) device coupled with the CPU (Swaine: par. [0102]: “system, comprising a number of CPUs 600, 615 and a GPU 620”), wherein the first I/O device (GPU 620) is configured to:
translate a first virtual address into a first physical address using a first translation agent associated with the first I/O device (Swaine: par. [0102]: “the GPU may also include its own internal MMU 630… in this instance the stage one address translation may be performed by the MMU 630, in order to convert a virtual address into an intermediate physical address”);
send a first address translation request to a second translation agent associated with the CPU, wherein the first address translation request comprises the first physical address; and receive a first address translation response from the second translation agent, the first address translation response comprising a second physical address, wherein the second physical address is associated with an address space of the system (Swaine: par. [0102]: “the SMMU 625 may then be used to perform a stage two address translation in order to translate the intermediate physical address into a final physical address within memory 645”; Taught as: GPU 620 e.g., first I/O device using an MMU 630 e.g., first translation agent, translates virtual address into the intermediate address, which then is sent as the first physical address to SMMU (e.g., second translation agent). The SMMU then translates the first physical/intermediate address to a system/second physical address associated with the memory 645).
As per claims 3 and 12, Swaine teaches wherein the second translation agent comprises an input/output memory management unit (IOMMU) or a system memory management unit (SMMU) (Swaine: fig. 11, item 625; par. [0102]).
As per claims 4 and 13, Swaine teaches wherein first I/O device comprises a graphics processing unit (GPU) and the first translation agent comprises a graphics memory management unit (GMMU) (Swaine: fig. 11, item 630; par. [0102]: the MMU 630 associated with GPU).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 6, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Swaine et al. (US 2024/0045802) as applied to claims 1 and 10 above, and further in view of Feero et al. (US 2025/0103492).
As per claims 5 and 14, Swaine fails to teach wherein the first I/O device includes a cache, and wherein the second physical address is used as a tag within the cache.
Feero teaches wherein the first I/O device includes a cache, and wherein the second physical address is used as a tag within the cache (Feero: par. [0045] teaches a coprocessor 120 (e.g., I/O device) comprising a physically tagged cache 160, means a physical address is used as cache tag). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide coprocessor with a physically tagged cache to improve the performance of the system because I/O device with cache improves the memory access performance and physically tagged cache simplifies the hardware management and prevent aliasing issues.
As per claims 6 and 15, Swaine and Feero teach wherein the cache of the first I/O device is coherent with one or more caches of the CPU (Swaine: par. [0103], Feero: par. [0037]).
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Swaine et al. (US 2024/0045802) as applied to claims 1 and 10 above, and further in view of Kaplan et al. (US 11,954,026).
As per claims 8 and 17, Swaine fails to teach wherein to translate the first virtual address into the first physical address using the first translation agent, the first I/O device is configured to: identify a page table of the first translation agent using a page directory base (PDB) identifier, wherein the page table serves a virtual machine (VM) of the system as indicated by the PDB identifier; and translate the first virtual address into the first physical address using the identified page table. Kaplan teaches a page directory base register corresponding to virtual machine pointing to the base address of the page table associated with corresponding virtual machine (Kaplan: col. 7, lines 22-43). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide PDB identifier for corresponding virtual machine to locate page table associated with the virtual machine to effectively identify particular page table for address translation associated with the virtual machine.
Allowable Subject Matter
Claims 2, 7, 9, 11, 16, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
As per claims 2, 11 and 20, prior arts of record fail to teach or suggest merging the first address translation response with one or more attributes obtained by the first translation agent, wherein the first address translation response further includes one or more attributes obtained from the second translation agent.
As per claims 7 and 16, prior arts of record fail to teach or suggest wherein the first address translation request is sent to the second translation agent in response to a determination that the first physical address is associated with a system memory of the CPU.
As per claims 9 and 18, prior arts of record fail to teach or suggest translate a second virtual address into a fabric linear address (FLA) using the first translation agent; determine that the FLA is associated with the second I/O device, wherein the second I/O device is a remote I/O device; send a second address translation request to the second I/O device, wherein the second address translation request contains the FLA; and receive a second address translation response from the second I/O device, the second address translation response comprising data associated with the FLA.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The examiner also requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 37 C.F.R. § 1.75(d) (1) requires such support in the Specification for any new language added to the claims and 37 C.F.R. § 1.83(a) requires support be found in the Drawings for all claimed features.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAUSHIKKUMAR M PATEL whose telephone number is (571)272-5536. The examiner can normally be reached Mon-Fri: 9:00 AM - 5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim T Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138