Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Miyatake et al. (US Pub # 2020/0312384).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Miyatake et al. teach an operation method of a memory, the operation method comprising: receiving a first active command and a first row address; starting a first mismatch compensation operation in a sense amplifier array for a normal cell array corresponding to the first row address and in a redundancy sense amplifier array for a redundancy cell array corresponding to the normal cell array (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0064, unit 635(0),635(1) are redundant sense amp array); determining to access the normal cell array based on the first row address and repair information; deactivating the redundancy sense amplifier array for the redundancy cell array in response to a determination that the normal cell array is to be accessed (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0064, unit 610(0)..610(6) are normal array); activating a word line of the normal cell array corresponding to the first row address; and sensing and amplifying, by the sense amplifier array for the normal cell array, data of memory cells corresponding to the activated word line (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0064).
Even though Miyatake et al. teach activating prime / normal array and redundant array sense amplifier by the compensation control circuits 310, 320 (see paragraph 0032), but silent exclusively about deactivating the redundancy sense amplifier array. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Miyatake et al. where compensation circuits are activated for compensating sense amplifier based on received address and location of prime / normal memory i.e. redundant array along with sense amp not accessed / deactivated during accessing of prime memory in order to improve reliability of memory device along with access time for the sense amp.(see paragraph 0003, 0005).
Regarding claim 2, Miyatake et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Miyatake et al. further teach, further comprising: receiving a precharge command; deactivating the activated word line in response to the precharge command; and deactivating the sense amplifier array for the normal cell array in response to the precharge command (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0060).
Regarding claim 3, Miyatake et al. teach all claimed subject matter as applied in prior rejection of claim 2 on which this claim depends.
Miyatake et al. further teach, further comprising: receiving a second active command and a second row address; starting a second mismatch compensation operation in a sense amplifier array for a normal cell array corresponding to the second row address and in the redundancy sense amplifier array for the redundancy cell array (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055); determining to access the redundancy cell array based on the second row address and the repair information; deactivating the sense amplifier array for the normal cell array in response to a determination that the redundancy cell array is to be accessed; activating a redundancy word line of the redundancy cell array; and sensing and amplifying, by the sense amplifier array for the redundancy cell array, data of memory cells corresponding to the activated redundancy word line (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0061).
Regarding claim 4, Miyatake et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Miyatake et al. further teach, the first mismatch compensation operation is performed in parallel in the sense amplifier array for the normal cell array corresponding to the first row address and in the redundancy sense amplifier array corresponding to the normal cell array (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0062).
Regarding claim 5, Miyatake et al. teach all claimed subject matter as applied in prior rejection of claim 3 on which this claim depends.
Miyatake et al. further teach, the second mismatch compensation operation is performed in parallel in the sense amplifier array for the normal cell array corresponding to the second row address and in the redundancy sense amplifier array (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0060).
Regarding independent claim 6, Miyatake et al. teach a memory comprising: a normal cell array; a normal sense amplifier array configured to sense and amplify data of the normal cell array; a redundancy cell array; a redundancy sense amplifier array configured to sense and amplify data of the redundancy cell array (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0064, unit 635(0),635(1) are redundant sense amp array); and a repair determination circuit configured to determine whether to access the redundancy cell array based on a row address and repair information (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0064, unit 155), wherein a mismatch compensation operation of the normal sense amplifier array and the redundancy sense amplifier array starts in response to an active command, and wherein, after the determination of the repair determination circuit, one of the normal sense amplifier array and the redundancy sense amplifier array is deactivated (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0064, unit 610(0)..610(6) are normal array, mismatch compensation control unit 310, 320).
Even though Miyatake et al. teach activating prime / normal array and redundant array sense amplifier by the compensation control circuits 310, 320 (see paragraph 0032), but silent exclusively about the redundancy sense amplifier array is deactivated. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Miyatake et al. where compensation circuits are activated for compensating sense amplifier based on received address and location of prime / normal memory i.e. redundant array along with sense amp not accessed / deactivated during accessing of prime memory in order to improve reliability of memory device along with access time for the sense amp.(see paragraph 0003, 0005).
Regarding claim 7, Miyatake et al. teach all claimed subject matter as applied in prior rejection of claim 6 on which this claim depends.
Miyatake et al. further teach, wherein, when the repair determination circuit determines to access the redundancy cell array: the redundancy sense amplifier array is deactivated; a word line of the normal cell array corresponding to the row address is activated; and the normal sense amplifier array senses and amplifies data of memory cells corresponding to the word line (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058).
Regarding claim 8, Miyatake et al. teach all claimed subject matter as applied in prior rejection of claim 6 on which this claim depends.
Miyatake et al. further teach, wherein, when the repair determination circuit determines to access the redundancy cell array: the normal sense amplifier array is deactivated; a redundancy word line of the redundancy cell array is activated; and the redundancy sense amplifier array senses and amplifies data of memory cells corresponding to the redundancy word line (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0061).
Regarding claim 9, Miyatake et al. teach all claimed subject matter as applied in prior rejection of claim 6 on which this claim depends.
Miyatake et al. further teach, further comprising: a normal row circuit is configured to drive word lines of the normal cell array; a normal sense amplifier array control circuit is configured to control the normal sense amplifier array; a redundancy row circuit is configured to drive redundancy word lines of the redundancy cell array; and a redundancy sense amplifier array control circuit is configured to control the redundancy sense amplifier array (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0063).
Regarding claim 10, Miyatake et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Miyatake et al. further teach, wherein, in response to the active command, the normal sense amplifier array control circuit controls the normal sense amplifier array to start the mismatch compensation operation and the redundancy sense amplifier array control circuit controls the redundancy sense amplifier array to start the mismatch compensation operation (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055), and wherein, in response to the determination of the repair determination circuit, one of the normal sense amplifier array control circuit and the redundancy sense amplifier array control circuit deactivates a sense amplifier array corresponding thereto (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0064).
Regarding claim 11, Miyatake et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Miyatake et al. further teach, wherein, in response to the determination of the repair determination circuit, one of the normal row circuit and the redundancy row circuit activates one of word lines corresponding thereto (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0054).
Regarding claim 12, Miyatake et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Miyatake et al. further teach, wherein, when access to the normal cell array is determined as a result of the determination of the repair determination circuit, the normal row circuit activates a word line selected by the row address among the word lines (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0060).
Regarding claim 13, Miyatake et al. teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Miyatake et al. further teach, wherein, when access to the redundancy cell array is determined as a result of the determination of the repair determination circuit, the redundancy row circuit activates a redundancy word line designated to replace a word line selected by the row address among the redundancy word lines (see Fig.1-6, paragraph 0014-0023, 0027-0040, 0043-0055, 0058-0064).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824