DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/16/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s) or using case law.
Claim(s) 1, 7, 8, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Otake (US 2020/0381518) in view of Liu (US 2026/0156858)
Regarding claim 1.
Otake teaches:
A nitride semiconductor module, comprising:
a chip including at least one transistor (fig 2:1; [para 0056]), wherein the chip includes:
a semiconductor substrate (fig 2:11; [para 0061]) including a substrate upper surface and a substrate lower surface facing an opposite side of the substrate upper surface;
an electron transit layer (fig 2:13; [para 0064]) formed over the substrate upper surface of the semiconductor substrate (fig 2:11; [para 0061]) and made of GaN ([para 0064]);
and an electron supply layer (fig 2:14; [para 0065]) formed over the electron transit layer (fig 2:13; [para 0064]) and made of GaN ([para 0065]) having a larger band gap than the electron transit layer (fig 2:13; [para 0065]), wherein the at least one transistor (fig 2:1; [para 0056]) includes a gate electrode (fig 2:24; [para 0070]), a source electrode (fig 2:3; [para 0058]), and a drain electrode (fig 2:4; [para 0059]), which are formed over the electron supply layer (fig 2:14; [para 0065]), and wherein the semiconductor substrate (fig 2:11; [para 0061]) is a GaN substrate having a thickness .
Otake does not teach the substrate thickness is 100 microns
Liu teaches:
A substrate (fig 5:1; [para 0030]) thickness of 100 microns ([para 0030])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a substrate thickness of 100 microns in order to reduce thermal and electrical resistance through the substrate.
Regarding claim 7
Otake in view of Liu teaches the nitride semiconductor module of claim 1, above
Otake teaches:
the electron transit layer (fig 2:13; [para 0064]) is a GaN layer, and wherein the electron supply layer (fig 2:14; [para 0065]) is an AlGaN layer.
Regarding claim 8
Otake in view of Liu teaches the nitride semiconductor module of claim 1, above
Otake teaches:
the at least one transistor (fig 2:1; [para 0056]) includes a gate layer (fig 2:21; [para 0071]) formed over the electron supply layer (fig 2:14; [para 0065]) and made of GaN containing an acceptor type impurity ([para 0071]), and wherein the gate electrode (fig 2:24; [para 0070]) is formed over the gate layer (fig 2:21; [para 0071])
Regarding claim 9
Otake in view of Liu teaches the nitride semiconductor module of claim 8, above
Otake teaches:
the electron transit layer (fig 2:13; [para 0064]) is a GaN layer, wherein the electron supply layer (fig 2:14; [para 0065]) is an AlGaN layer, and wherein the gate layer is a GaN layer (fig 2:21; [para 0071]) containing the acceptor type impurity.
Regarding claim 10.
Otake in view of Liu teaches the nitride semiconductor module of claim 1, above
Otake teaches:
a control circuit (fig 6:102; [para 0080]) configured to control an on/off operation of the at least one transistor (fig 2,6:1,101; [para 0080,0087]).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Otake (US 2020/0381518) in view of Liu (US 2026/0156858) as applied to claim 1 and further in view of Leong (US 2023/0282638)
Regarding claim 2.
Otake in view of Liu teaches the nitride semiconductor module of claim 1, above
Otake in view of Liu does not teach a plurality of transistors.
Leong teaches:
the at least one transistor includes a plurality of transistors (fig 2:122,124; [para 0020]), and wherein the chip (fig 2:8a; [para 0020]) includes the plurality of transistors (fig 2:122,124; [para 0020]),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide multiple transistors in the chip in order to form a bidirectional switch device for AC switching (paragraph 1)
Claim(s) 3, 4, and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Otake (US 2020/0381518) in view of Liu (US 2026/0156858) as applied to claim 1 and further in view of Yu (US 2023/0083337)
Regarding claim 3.
Otake in view of Liu teaches the nitride semiconductor module of claim 1, above
Otake in view of Liu does not teach a sealing member
Yu teaches:
a sealing member (fig 10:40; [para 0072]) configured to cover the chip (fig 10:10; [para 0071]), wherein the nitride semiconductor module (fig 10:2; [para 0072])includes a module upper surface formed of the sealing member (fig 10:40; [para 0072]) and facing a same side as the substrate upper surface, and a module lower surface formed of the sealing member and facing a same side as the substrate lower surface (fig 10), and wherein a thickness (fig 10:h2; [para 0073]) of the semiconductor substrate (fig 8:110; [para 0039]) is thinner than a distance from an upper surface of the electron supply layer (fig 8:123; [para 0049]) to the module upper surface (fig 8,10).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a sealing member in order to protect the semiconductor device from damage and the environment
Regarding claim 4.
Otake in view of Liu teaches the nitride semiconductor module of claim 1, above
Otake in view of Liu does not teach a sealing member
Yu teaches:
a sealing member (fig 10:40; [para 0072]) configured to cover the chip (fig 10:10; [para 0071]), wherein the nitride semiconductor module (fig 10:2; [para 0072]) includes a module upper surface formed of the sealing member (fig 10:40; [para 0072]) and facing a same side as the substrate upper surface, and a module lower surface formed of the sealing member and facing a same side as the substrate lower surface, and wherein a chip lower surface of the chip (fig 10:10; [para 0071]) is located closer to the module lower surface than the module upper surface in a thickness direction of the semiconductor substrate.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a sealing member in order to protect the semiconductor device from damage and the environment
Regarding claim 5.
Otake in view of Liu teaches the nitride semiconductor module of claim 1, above
Otake in view of Liu does not teach a sealing member
Yu teaches:
a sealing member (fig 10:40; [para 0072]) configured to cover the chip (fig 10:10; [para 0071]), wherein the nitride semiconductor module (fig 10:2; [para 0072]) includes a module upper surface formed of the sealing member (fig 10:40; [para 0072]) and facing a same side as the substrate upper surface, and a module lower surface formed of the sealing member (fig 10:40; [para 0072]) and facing a same side as the substrate lower surface, and wherein the nitride semiconductor module (fig 10:2; [para 0072]) further comprises a heat dissipation member (fig 10:80; [para 0058]) installed at the substrate lower surface and exposed to the module lower surface (fig 10).
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Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Otake (US 2020/0381518) in view of Liu (US 2026/0156858) in view of Yu (US 2023/0083337) as applied to claim 5 and further in view of Kinzer (US 2016/0247748)
Regarding claim 6.
Otake in view of Liu in view of Yu teaches
The nitride semiconductor module of claim 5, above
Otake in view of Liu in view of Yu does not teach the heat dissipation member has a thickness of 150 μm or less.
Kinzer teaches:
the heat dissipation member (fig 7b:205; [para 0060]) has a thickness of 150 μm or less ([para 0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the thickness of the member to be less than 150 microns in order to minimize package size and material used in the process
Given the teaching of the references, it would have been obvious to determine the optimum thickness of the heat dissipation layer for the purpose of heat dissipation and electrical connection. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Otake (US 2020/0381518) in view of Liu (US 2026/0156858) in view of Leong (US 2023/0282638) as applied to claim 2 and further in view of Escudero Rodrguez (US 2019/0052167)
Regarding claim 11.
Otake in view of Liu in view of Leong teaches the nitride semiconductor module of claim 1, above
Otake in view of Liu in view of Leong does not teach a bridge circuit.
Escudero Rodriguez teaches:
a bridge circuit configured by using the plurality of transistors (fig 2; [para 0023]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate with a bridge circuit in order to form a bidirectional phase-shift full bridge converters in which induced voltage overshoot in the reverse direction (boost mode) is mitigated (paragraph 21).
Regarding claim 12.
Otake in view of Liu in view of Leong in view of Escudero Rodriguez teaches the nitride semiconductor module of claim 11,
Otake teaches:
and wherein the nitride semiconductor module further comprises a control circuit (fig 6:102; [para 0080]) configured to control on/off operations (fig 2,6:1,101; [para 0080,0087]).
.
Escudero Rodriguez teaches:
wherein the plurality of transistors constitute a half-bridge circuit including a high-side transistor and a low-side transistor connected in series with each other, and further comprises a control circuit configured to control on/off operations of the high-side transistor and the low-side transistor (paragraph 23).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate with a bridge circuit in order to form a bidirectional phase-shift full bridge converters in which induced voltage overshoot in the reverse direction (boost mode) is mitigated (paragraph 21).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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